公开(公告)号：DE10051173A1

公开(公告)日：2002-04-25

申请号：DE10051173

申请日：2000-10-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  ROEHR THOMAS ,  BOEHM THOMAS

IPC: G11C11/15

Abstract: Both ends of a selected word line (WL2) are set at a high voltage (V2) to keep the voltage drop on the selected word line as low as possible. A cell (Z22) is read out at an intersecting point between the selected word line and a bit line. Other word lines are set at another voltage level. An Independent claim is also included for a method for reducing the voltage drop along a word/bit line in an MRAM memory.

公开(公告)号：DE10042222A1

公开(公告)日：2002-03-14

申请号：DE10042222

申请日：2000-08-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  BOEHM THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/22

Abstract: The CFRAM arrangement has a number of memory cells each consisting of a ferroelectric storage capacitor and a selection transistor. Each block of selection transistors is associated with a block-select-transistor. The selection transistors and the block-select-transistor are arranged between a plate line and a bit line and the selection transistors are each connected to word lines. The selection transistors are depletion type FETs. The CFRAM arrangement has a number of memory cells (Z0-Z3) each consisting of a ferroelectric storage capacitor (Cferro0...) and a selection transistor (Tdep10..). Each block of selection transistors is associated with a block-select-transistor (TEnh). The selection transistors and the block-select-transistor are arranged between a plate line (PL) and a bit line (BL) and the selection transistors are each connected to word lines (WL0...). The selection transistors are depletion type field effect transistors.

公开(公告)号：DE10034083C1

公开(公告)日：2002-03-14

申请号：DE10034083

申请日：2000-07-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C7/18 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  H01L27/10 ,  H01L23/528

Abstract: A memory matrix based on at least one cell array of column lines and row lines in which at least two column- or row-lines change their location relative to one another i.e. they cross-over one another. The memory matrix has cell arrays stacked in layers one above the other, and in which in each case the column- or row-lines of different layers lie mainly mutually adjacent, opposite one another.

公开(公告)号：DE10032272A1

公开(公告)日：2002-01-24

申请号：DE10032272

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  MUELLER GERHARD ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A bit line (BL) first driver (FD) (T1) has an FD current source (J3) and an FD n-channel field effect transistor (N6) with a channel width (wn). The FD current source and the FD field effect transistor connect in series between a BL source of voltage supply (V-SupplyBL) and the BL. A second driver (SD) (T2) for a word line (WL) has an SD current source (J0) that connects with an SD field effect transistor (N0) in series between a WL source of voltage supply (V-SupplyWL) and the WL.

公开(公告)号：DE10057806B4

公开(公告)日：2007-10-11

申请号：DE10057806

申请日：2000-11-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ ,  DEHM CHRISTINE

IPC: H01L21/8239 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged using the stacking principle, and both capacitor electrodes, which are located one above the other, of each memory cell are directly electrically connected by means of contact plugs to corresponding source and drain regions of an associated selection transistor in the substrate. Contact plugs for the contact connection to the upper capacitor electrodes are produced from above the configuration.

公开(公告)号：DE102005031892A1

公开(公告)日：2007-01-04

申请号：DE102005031892

申请日：2005-07-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  WILLER JOSEF

IPC: G11C16/12 ,  G11C16/10 ,  G11C16/24

Abstract: A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired programming of a neighboring memory cell is avoided by the application of an intermediate inhibit voltage to an adjacent bitline. This is done by precharging all the bitlines to the inhibit voltage, either by successively applying the inhibit voltage to every bitline individually or by applying both the upper and the lower programming voltage to one half of the bitlines and then short-circuiting all the bitlines to produce an intermediate voltage.

公开(公告)号：DE102005008392A1

公开(公告)日：2006-09-07

申请号：DE102005008392

申请日：2005-02-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  BRUCHHAUS RAINER

IPC: H01L27/105 ,  G11C11/22

Abstract: The unit has a ferro electric region (4) extending in a section between capacitor electrodes. Another region extends in another section between the former and other two electrodes. Two areas are arranged such that two coercive voltages and remanent polarization in respective sections are different so that a capacitor structure formed by the electrodes has a level hysteresis characteristic in a polarization-voltage characteristics cure. Independent claims are also included for the following: (1) a ferroelectric random access memory circuit for storing of data with a ferroelectric memory unit (2) a method for storing of data in a ferroelectric memory unit.

公开(公告)号：DE102005001667A1

公开(公告)日：2006-07-27

申请号：DE102005001667

申请日：2005-01-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS

IPC: G11C16/00

Abstract: The cell has a selection unit (6) activated to provide data depending on different conductivity conditions of resistive memory units (4, 5) for storing the data in a memory unit (1). A control unit (9) activates the selection unit so that the data is stored in the unit (1). The control unit deactivates the selection unit after storing the data in the unit (1) so that the memory units (4, 5) are separated from the memory unit (1).

公开(公告)号：DE102004059035A1

公开(公告)日：2005-07-14

申请号：DE102004059035

申请日：2004-12-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  JACOB MICHAEL

IPC: G11C7/02 ,  G11C7/08 ,  G11C7/18 ,  G11C8/12 ,  G11C11/22 ,  H01L27/105

公开(公告)号：DE102004028340A1

公开(公告)日：2005-01-27

申请号：DE102004028340

申请日：2004-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JACOB MICHAEL ,  ROEHR THOMAS ,  WOHLFAHRT JOERG

IPC: G06F11/10 ,  G11C29/00

Abstract: Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.