公开(公告)号：JP2001237393A

公开(公告)日：2001-08-31

申请号：JP2000399178

申请日：2000-12-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER DR ,  KASTNER MARCUS ,  DEHM CHRISTINE

IPC: H01L21/316 ,  H01L21/02 ,  H01L21/318 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a ferroelectric memory. SOLUTION: A switching resistor (2) is formed on a semiconductor substrate (1), an isolation layer (4) is deposited on the switching transistor (2), and then a memory capacitor provided with a lower electrode (7) formed of platinum and a ferroelectric or paraelectric (8) is formed on the isolation layer. In order to protect the dielectric against intrusion of hydrogen in following manufacturing processes, a first barrier layer (5) is embedded in the isolation layer (4) and, after formation of the memory capacity, a second barrier layer (10) connected to the first barrier layer (5) is deposited.

公开(公告)号：WO0001010A3

公开(公告)日：2002-10-03

申请号：PCT/DE9901770

申请日：1999-06-16

Applicant: INFINEON TECHNOLOGIES AG ,  ROEHR THOMAS ,  MAZURE-ESPEJO CARLOS ,  DEHM CHRISTINE

Inventor： ROEHR THOMAS ,  MAZURE-ESPEJO CARLOS ,  DEHM CHRISTINE

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/033

CPC classification number: H01L28/60 ,  H01L21/32139 ,  H01L2924/0002 ,  Y10S438/95 ,  H01L2924/00

Abstract: Disclosed is a method for producing semiconductor elements comprising a metal layer (10) arranged on a semiconductor substrate . The inventive method consists of the following steps: a silicon layer (30) is deposited on a metal layer (10); an etch mask is applied in order to structure the silicon layer (30); the silicon layer is selectively etched (30) using said etch mask (25); and the metal layer (10) is structured in an etching process using a selectively etched silicon layer (30) as a hard mask.

Abstract translation: 提出一种包括用于制造半导体器件的方法的步骤具有布置在半导体衬底金属层上（10）：所述金属层（10）上沉积硅层（30）; 施加的蚀刻掩模（25），用于图案化所述硅层（30）; 选择性地蚀刻使用蚀刻掩模（25）的硅层（30）; 以及使用该选择性地蚀刻硅层（30）作为硬掩模在蚀刻工艺图案化所述金属层（10）。

公开(公告)号：WO2006021483A3

公开(公告)日：2006-10-05

申请号：PCT/EP2005053779

申请日：2005-08-03

Applicant: INFINEON TECHNOLOGIES AG ,  HALIK MARCUS ,  DEHM CHRISTINE ,  KLAUK HAGEN ,  ZSCHIESCHANG UTE ,  SCHMID GUENTER

Inventor： HALIK MARCUS ,  DEHM CHRISTINE ,  KLAUK HAGEN ,  ZSCHIESCHANG UTE ,  SCHMID GUENTER

IPC: H01L51/10 ,  H01L27/28

CPC classification number: H01L51/0545 ,  H01L21/312 ,  H01L27/3244

Abstract: The invention relates to a semiconductor circuit arrangement (10) and to a method for the production thereof, in which a protective material region (50) made of poly(para-xylene) is formed for the material separation of a first circuit region (30) and a second circuit region (40).

Abstract translation: 提出了一种半导体电路装置（10）和它们的制备方法，其中的第一电路部分（30）和聚（对 - 二甲苯）的保护材料区（50）的第二电路部分（40）的物理分离形成或为。

公开(公告)号：DE10212962A1

公开(公告)日：2003-10-16

申请号：DE10212962

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMID GUENTER ,  HALIK MARCUS ,  KLAUK HAGEN ,  DEHM CHRISTINE ,  HANEDER THOMAS ,  MIKOLAJICK THOMAS

IPC: G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L51/20 ,  H01L51/30 ,  G11C11/21

Abstract: A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region that includes or is made of an organic semiconductor material. Besides a first gate electrode of the gate electrode configuration of the field-effect transistor device, an additional selection gate electrode is provided, by way of which the field-effect transistor device can be switched off without influencing the storage dielectric and independently of the first gate electrode.

公开(公告)号：DE10212926A1

公开(公告)日：2003-10-16

申请号：DE10212926

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMID GUENTER ,  HALIK MARCUS ,  KLAUK HAGEN ,  DEHM CHRISTINE ,  HANEDER THOMAS ,  MIKOLAJICK THOMAS

IPC: G11C11/56 ,  G11C13/02 ,  H01L27/10 ,  H01L29/78 ,  H01L27/115

Abstract: Semiconductor storage cell has a modulation region (M) arranged between first gate electrode (G1) of gate electrode arrangement,and an insulating region. (M) is made from a material which can be controllably modulated with respect to its electrical and/or its wide material properties between at least two states. The channel region can be electromagnetically influenced according to the states of the modulation material, especially when there is an electrical potential difference between the first gate electrode and the source/drain regions (SD1, SD2). The electrical conductivity of the channel region can be controlled via the states of the modulation material and/or via the state changes. The modulation region is made from an organic and/or inorganic material, especially in the form of a mono-layer.

公开(公告)号：DE19833448C2

公开(公告)日：2003-07-17

申请号：DE19833448

申请日：1998-07-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRITSCH ELKE ,  DEHM CHRISTINE ,  WENDT HERMANN ,  WEINRICH VOLKER

IPC: H01L21/302 ,  C23C16/44 ,  H01L21/205 ,  H01L21/3065 ,  C23F4/00

Abstract: A cleaning process for cleaning CVD units is disclosed. In the cleaning process, alkaline earth metal and/or metal-containing process residues, which form an amorphous film on reactor walls, are removed using a dry etching medium containing free diketones at a greatly reduced pressure and an elevated temperature. In the process, the free diketones react with the alkaline earth metals or metals to form volatile complexes.

公开(公告)号：DE10053170C2

公开(公告)日：2002-09-26

申请号：DE10053170

申请日：2000-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SITARAM ARKALGUD ,  MAZURE CARLOS ,  DEHM CHRISTINE

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/11507 ,  H01L27/105 ,  H01L21/8239

公开(公告)号：DE10053170A1

公开(公告)日：2002-05-16

申请号：DE10053170

申请日：2000-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SITARAM ARKALGUD ,  MAZURE CARLOS ,  DEHM CHRISTINE

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/11507 ,  H01L27/105 ,  H01L21/8239

公开(公告)号：DE19935131A1

公开(公告)日：2001-02-08

申请号：DE19935131

申请日：1999-07-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERGMANN RENATE ,  DEHM CHRISTINE ,  HASLER BARBARA ,  SCHELER ULRICH ,  SCHINDLER GUENTHER ,  WEINRICH VOLKER ,  HARTNER WALTER

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/8239 ,  H01L27/08

Abstract: The invention relates to a method for removing redepositions on a wafer and to a wafer which is devoid of redepositions. The removal of the redepositions on the wafer occurs after a protective layer is arranged on the top electrode and the boundary surfaces of the electrodes with a dielectric, whereby said areas are not damaged by wet chemical agents enabling the redepositions to be exclusively and efficiently removed.

公开(公告)号：DE102004051152A1

公开(公告)日：2006-05-04

申请号：DE102004051152

申请日：2004-10-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFFMANN KURT ,  DEHM CHRISTINE ,  SEZI RECAI ,  WALTER ANDREAS

IPC: G11C13/00 ,  G11C5/06 ,  G11C7/18 ,  H01L27/06 ,  H01L27/105 ,  H01L45/00

Abstract: A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.