公开(公告)号：ITTO990798A1

公开(公告)日：2001-03-19

申请号：ITTO990798

申请日：1999-09-17

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  SACCO ANDREA ,  SCOTTI MARCO

IPC: H03K19/003

公开(公告)号：ITTO20000892D0

公开(公告)日：2000-09-22

申请号：ITTO20000892

申请日：2000-09-22

Applicant: ST MICROELECTRONICS SRL

Inventor： SACCO ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO ,  MICHELONI RINO

IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

公开(公告)号：ITMI20001585D0

公开(公告)日：2000-07-13

申请号：ITMI20001585

申请日：2000-07-13

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  TORELLI GUIDO ,  MICHELONI RINO ,  PIERIN ANDREA ,  GREGORI STEFANO ,  SANGALLI MIRIAM

IPC: G11C16/08

Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.

公开(公告)号：ITTO990993D0

公开(公告)日：1999-11-16

申请号：ITTO990993

申请日：1999-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C11/56 ,  G11C16/30

Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.

公开(公告)号：DE602004026707D1

公开(公告)日：2010-06-02

申请号：DE602004026707

申请日：2004-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： MARELLI ALESSIA ,  RAVASIO ROBERTO ,  MICHELONI RINO

IPC: H03M13/15 ,  G06F11/10

Abstract: The invention relates to a method and system for correcting errors in multilevel memories using binary BCH codes. The number of errors is estimated by analyzing the syndrome components (5). If the number of estimated errors is one, then simple decoding for a Hamming code is performed. Otherwise, conventional decoding of the BCH code is carried out (2,3). This avoids the computation of the error locator polynomial and its roots in the presence of only one error and, thus, reduces the average decoding complexity.

公开(公告)号：DE602006012011D1

公开(公告)日：2010-03-18

申请号：DE602006012011

申请日：2006-03-21

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

IPC: H03K17/10 ,  G11C16/12 ,  H01L27/02

Abstract: A circuit is disclosed. The circuit comprises a first input terminal (INA1), a second input terminal (INA2) and an output terminal (OUT). The circuit further includes a first circuital branch (610) connected between the first input terminal and the output terminal, and a second circuital branch (620) connected between the second input terminal and the output terminal. The first circuital branch is selectively activatable for coupling the first input terminal with the output terminal, and the second circuital branch is selectively activatable for coupling the second input terminal with the output terminal. The first and second circuital branches comprise each at least one electronic device having at least a first and a second device terminals. Said at least one electronic device is designed to guarantee the capability of sustaining voltage differences across at least the first and second device terminals thereof that are up-limited in absolute value by a first predetermined maximum value lower than the maximum of absolute values of voltage differences between the output terminal and the first input terminal, and between the output terminal and the second input terminal, respectively.

公开(公告)号：DE60327032D1

公开(公告)日：2009-05-20

申请号：DE60327032

申请日：2003-10-23

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

IPC: G11C11/00

Abstract: A semiconductor memory comprises a plurality of memory cells (MC), for example Flash memory cells, arranged in a plurality of lines (LBL), and a plurality of memory cell access signal lines (MBL), each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance (CMBL) intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.

公开(公告)号：DE602005012682D1

公开(公告)日：2009-03-26

申请号：DE602005012682

申请日：2005-07-22

Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS SRL

Inventor： CRIPPA LUCA ,  MISSIROLI CHIARA ,  MICHELONI RINO

IPC: G11C16/26 ,  G11C16/04

Abstract: A reading method of a NAND memory device including the steps of: first connecting a first end terminal (12a) of a stack (12) of cells (3, 3', 3") to a reference line (13); second connecting a second end terminal (12b) of the stack (12) of cells (3, 3', 3") to a respective bitline (10); charging the bitline (10) to a predetermined bitline read voltage (V DR ), wherein one of the steps of first connecting and second connecting is carried out before charging the bitline (10) and the other of the steps of first connecting and second connecting is carried out after charging the bitline (10). An order of carrying out the steps of first connecting and second connecting is determined based on an address (MSB; AL2) of a selected cell (3', 3") .

公开(公告)号：DE602005012625D1

公开(公告)日：2009-03-19

申请号：DE602005012625

申请日：2005-07-22

Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS SRL

Inventor： BOVINO ANGELO ,  ALTIERI VINCENZO ,  RAVASIO ROBERTO ,  MICHELONI RINO ,  DE MATTEIS MARIO

IPC: G11C11/56

Abstract: Multi-level programming (30-42) allows for writing a first and a second bit in selected cells (3) by separately programming (30-32) a first bit (LSB) from a second bit (MSB). Programming (30-32) of the first bit determines a shifting (32) from a first threshold level (A) to a second threshold level (B); programming (36-42) of the second bit requires a preliminary reading (36-40) to detect whether the first bit (LSB) has been modified; performing a first writing step (42) to bring the cell to a third threshold voltage (C) if the first bit has been modified and performing a second writing step (42) to bring the selected cell to a fourth threshold voltage (D) different from the third threshold level if the first bit has not been modified. The memory array (2) divided into a first portion (2a) where data are stored using multiple threshold levels corresponding to a plurality of bits, and a second portion (2b) where data are stored using two threshold levels corresponding to a single bit. For increasing reading and program reliability, during preliminary reading (40) of the second portion (2b) a reading result is forced to correspond to the first threshold level.

公开(公告)号：DE60129786T2

公开(公告)日：2008-04-30

申请号：DE60129786

申请日：2001-01-15

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

IPC: G11C11/56 ,  G11C7/06 ,  G11C16/06 ,  G11C16/02 ,  G11C16/26

Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell (36) by a capacitive element (22, 23). The capacitive element (22, 23) is initially charged and then discharged linearly in a preset time, while the memory cell (36) is biased at a constant voltage. In a first operating mode, initially a first capacitor (22) and a second capacitor (23) are respectively charged to a first charge value and to a second charge value. The second capacitor (23) is discharged through the memory cell (36) at a constant current in a preset time; the first charge is shared between the first capacitor (22) and the second capacitor (23); and then the shared charge is measured.