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公开(公告)号：EP0814481B1
公开(公告)日：2002-03-20
申请号：EP96830345.3
申请日：1996-06-18
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Micheloni, Rino , Commodaro, Stefano
IPC: G11C16/06
CPC classification number: G11C16/08
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公开(公告)号：EP1126614A1
公开(公告)日：2001-08-22
申请号：EP00830102.0
申请日：2000-02-14
Applicant: STMicroelectronics S.r.l.
Inventor： Ghezzi, Stefano , Ferrario, Donato , Yero, Emilio , Campardo, Giovanni
IPC: H03K19/177
CPC classification number: H03K19/17736 , H03K19/17704 , H03K19/1778 , Y10T307/505
Abstract: A programmable logic array (PLA) has at least an AND plane comprising an array of transistors arranged in rows and columns, the transistors belonging to a same column being connected in series with each other, the two end current terminals of said series of transistors being coupled to the supply voltage rail (VDD) and to a reference (GND), respectively, the transistors of the first row and of the last row of the array having their control terminals coupled to respective opposite enabling/disabling potentials. To each row of said array, with the exception of the first and the last row, are associated three control lines, the first line being coupled to a first input value, the second line being coupled to the inverted logic value of the first input value and the third line being coupled to a voltage sufficient to keep in a state of conduction the transistors of the row connected to it. Each transistor of each row except the first and the last row has its control terminal connected to one of the three control lines associated to the row.
An OR plane comprises at least an array of transistors arranged in rows and columns, the transistors belonging to a same column having their respective control terminals connected to a control line and a first current terminal coupled to a reference potential (GND), each transistor of each row of the array having a second current terminal connected or not to a respective output line. The second current terminal of each transistor of the array that is not connected to a respective output line is short-circuited to the first current terminal of the same transistor.Abstract translation: 可编程逻辑阵列（PLA）具有至少一个AND平面，其包括以行和列排列的晶体管阵列，属于同一列的晶体管彼此串联连接，所述一系列晶体管的两个端电流端子 耦合到电源电压轨（VDD）和参考（GND），阵列的第一行和最后一行的晶体管的控制端分别耦合到相应的使能/禁止电位。 除了第一行和最后一行之外，对于所述阵列的每一行都关联三个控制线，第一行耦合到第一输入值，第二行耦合到第一输入值的反相逻辑值 并且第三线被耦合到足以保持处于与其连接的行的晶体管的导通状态的电压。 除了第一行和最后一行之外，每行的每个晶体管的控制端连接到与行相关联的三条控制线之一。 OR平面包括至少排列成行和列的晶体管阵列，属于相同列的晶体管的各自的控制端子连接到控制线和耦合到参考电位（GND）的第一电流端子，每个晶体管 阵列的每一行具有连接到或不连接到相应输出线的第二电流端子。 未连接到相应输出线的阵列的每个晶体管的第二电流端子与同一晶体管的第一电流端短路。
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公开(公告)号：EP1071096A1
公开(公告)日：2001-01-24
申请号：EP99830469.5
申请日：1999-07-22
Applicant: STMicroelectronics S.r.l.
Inventor： Micheloni, Rino , Campardo, Giovanni , Crippa, Luca
CPC classification number: G11C16/28
Abstract: The read circuit (1') comprises an array branch (6) having an input array node (22) connected, via an array bit line (8), to an array cell (10); a reference branch (12) having an input reference node (32) connected, via a reference bit line (14), to a reference cell (16); a current-to-voltage converter (18) connected to an output array node (56) of the array branch (6) and to an output reference node (58) of the reference branch (12) to supply on the output array node (56) and the output reference node (58) the respective electric potentials (V M , V R ) correlated to the currents flowing in the array memory cell (10) and, respectively, in the reference memory cell (16); and a comparator (19) connected at input to the output array node (56) and output reference node (58) and supplying as output a signal (OUT) indicative of the contents stored in the array memory cell (10); and an array decoupling stage (80) arranged between the input array node (22) and the output array node (56) to decouple the electric potentials of the input and output array nodes (22, 56) from one another.
Abstract translation: 读取电路（1'）包括具有通过阵列位线（8）连接到阵列单元（10）的输入阵列节点（22）的阵列分支（6）。 具有通过参考位线（14）连接到参考单元（16）的输入参考节点（32）的参考分支（12）; 连接到阵列分支（6）的输出阵列节点（56）和参考分支（12）的输出参考节点（58）的电流 - 电压转换器（18），以在输出阵列节点 56）和输出参考节点（58）分别与在阵列存储单元（10）中流动的电流和参考存储单元（16）相关的电位相关联的各个电位（VM，VR）; 以及比较器（19），其在输入端连接到输出阵列节点（56）和输出参考节点（58），并且作为输出提供指示存储在阵列存储单元（10）中的内容的信号（OUT）。 以及布置在所述输入阵列节点（22）和所述输出阵列节点（56）之间的阵列解耦级（80），以将所述输入和输出阵列节点（22,56）的电位彼此去耦。
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84.发明授权Reference signal generating method and circuit for differential evaluation of the content of non-volatile memory cells 失效方法和电路，用于产生参考信号以非易失性存储器单元的内容的差分评价
公开(公告)号：EP0676768B1
公开(公告)日：2000-12-27
申请号：EP94830143.7
申请日：1994-03-28
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Dallabora, Marco
IPC: G11C16/06
CPC classification number: G11C16/3445 , G11C16/28 , G11C16/344
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85.发明公开Row decoder for a nonvolatile memory with possibility of selectively biasing word lines to positive or negative voltages 有权行解码器，用于非易失性存储器为字线随机正和负偏置调整
公开(公告)号：EP1061525A1
公开(公告)日：2000-12-20
申请号：EP99830378.8
申请日：1999-06-17
Applicant: STMicroelectronics S.r.l. , Mitsubishi Electric Corporation
Inventor： Micheloni, Rino , Campardo, Giovanni , Ohba, Atsushi, c/o Mitsubishi Denki K. K. , Carrera, Marcello
Abstract: The row decoder includes, for each word line (WL) of the memory (2), a respective biasing circuit (54) receiving at the input a row selection signal (SR ) switching, in preset operating conditions, between a supply voltage (V CC ) and a ground voltage (V GND ) and supplying at the output a biasing signal (R ) for the respective word line (WL) switching between a first operating voltage (V PC ), in turn switching at least between the supply voltage (V CC ) and a programming voltage (V PP ) higher than the supply voltage (V CC ), and a second operating voltage (V NEG ), in turn switching at least between the ground voltage (V GND ) and an erase voltage (V ERN ) lower than the ground voltage (V GND ). Each biasing circuit (54) includes a level translator circuit (58) receiving at the input the row selection signal (SR ) and supplying as output a control signal (CM ) switching between the first and the second operating voltages (V PC , V NEG ) and an output driver circuit (60) receiving as input the control signal (CM ) and supplying at the output the biasing signal (R ).
Abstract translation: 行译码器包括，用于存储器（2），一个respectivement偏置电路（54）的每个字线（WL）在所述输入端接收一个行选择信号（SR的）的切换，在预先设定的操作条件下，一个电源之间 电压（VCC）和地电压（V GND），并在输出端供给的respectivement字线的第一工作电压（VPC）之间进行切换的偏置信号（R ）（WL），依次之间至少切换 电源电压（VCC）和一个编程电压（VPP）高于电源电压（VCC），和第二操作电压（VNEG），继而至少接地电压（V GND）和擦除电压（VERN）低之间切换更高 比接地电压（V GND）。 每个偏置电路（54）包括：在输入端接收所述行选择信号（SR的）和供应作为输出的控制信号的电平转换电路（58）（CM的）在第一和第二工作电压之间的切换 （VPC，VNEG）和接收作为输入的控制信号输出驱动器电路（60）（CM的），并在输出端供给所述偏压信号（R ）。
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Patent Agency Ranking86.发明公开CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching 有权CMOS开关期间在非易失性存储器的低功耗切换用于传输高电压，特别是对行译码器
公开(公告)号：EP1058271A1
公开(公告)日：2000-12-06
申请号：EP99830345.7
申请日：1999-06-04
Applicant: STMicroelectronics S.r.l. , Mitsubishi Electric Corporation
Inventor： Micheloni, Rino , Campardo, Giovanni , Ohba, Atsushi, c/o Mitsubishi Denki K. K. , Carrera, Marcello
IPC: G11C16/12 , H03K19/017
CPC classification number: H03K19/018521 , G11C5/145 , G11C8/10 , G11C11/5621 , G11C16/08 , H03K19/0013 , H03K19/01721
Abstract: The switch circuit (40) receives a first supply voltage (V CC ) and a second supply voltage (V PP ) different from each other; a control input (41a) receiving a control signal that may be switched between the first supply voltage and ground; a driving inverter stage (44) supplied by the second supply voltage (V PP ) and defining the output (70) of the circuit; a feedback inverter stage (43) supplied by the second supply voltage and including a top transistor (51) and a bottom transistor (53) defining an intermediate node (58) and having respective control terminals. The control terminal of the top transistor (51) is connected to the output node (70), the control terminal of the bottom transistor (53) is connected to the control input (41a), and the intermediate node is connected to the input (58) of the driving inverter stage. An activation element (80, 71) helps switching of the intermediate node (58) from the second supply voltage to ground; current limiting transistors (52, 62) are arranged in the inverter stages to limit the current flowing during switching and to reduce the consumption of the circuit.
Abstract translation: 开关电路（40）接收第一供给电压（VCC）和第二电源电压（VPP）从海誓山盟不同; 接收控制信号的控制输入端（41）可以被切换所述第一电源电压和地之间做; 由第二电源电压（VPP）和，定义电路的输出（70）提供的驱动逆变器级（44）; 由第二电源电压供电，并且包括一个顶部晶体管（51）和上限定中间节点（58）和具有respectivement控制端子的底部晶体管（53）的反馈逆变器级（43）。 顶部晶体管的控制端子（51）被连接到被连接到控制输入端（41A）和中间节点的输出节点（70），底部晶体管的控制端子（53）被连接到输入端（ 驱动用逆变器级的58）。 致动元件（80，71）可帮助从所述第二电源电压到地的中间节点（58）的切换; 限流晶体管（52，62）被布置在所述逆变器级，以限制流过的电流在开关期间，并减少了电路的功耗。
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87.发明公开Circuit device for providing a hierarchical row decoding in semiconductor memory devices 有权萨尔瓦多桑诺·祖尔等级Zellendekodierung einer Halbleiterspeicheranordnung
公开(公告)号：EP0991075A1
公开(公告)日：2000-04-05
申请号：EP98830570.2
申请日：1998-09-30
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Micheloni, Rino
IPC: G11C8/00
CPC classification number: G11C16/0416 , G11C8/14
Abstract: The invention relates to a circuit device for carrying out a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and comprising at least one matrix of memory cells (5) with sectors (3,4) organized into columns, wherein each sector has a specific group of local word lines (LWL) individually connected to a main word line (MWL) running through all of the matrix sectors which have rows in common. The device comprises a first transistor (M1) of the PMOS type having its conduction terminals connected, the one to the main word line (MWL) and the other to the local word line (LWL), and a second transistor (M3) of the NMOS type having its conduction terminals connected, the one to the local word line (LWL) and the other to a reference voltage (GND).
Abstract translation: 本发明涉及一种用于在非易失性类型的半导体存储器件中执行行解码的分层形式的电路装置，并且包括至少一个具有组织成列的扇区（3,4）的存储器单元（5）的矩阵，其中 每个扇区具有单独连接到贯穿所有具有公共行的矩阵扇区的主字线（MWL）的特定组的本地字线（LWL）。 该器件包括PMOS型的第一晶体管（M1），其导通端子连接到主字线（MWL），另一端连接到本地字线（LWL），第二晶体管（M3） 其导体端子连接的NMOS类型，一个连接到本地字线（LWL），另一个连接到参考电压（GND）。
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88.发明公开Row decoder circuit for an electronic memory device, particularly for low voltage applications 失效行解码器，用于电子存储器装置，特别是用于低压供电
公开(公告)号：EP0928003A3
公开(公告)日：2000-01-12
申请号：EP98114061.9
申请日：1998-07-28
Applicant: STMicroelectronics S.r.l.
Inventor： Micheloni, Rino , Campardo, Giovanni , Ferrario, Donato , Ghezzi, Stefano
IPC: G11C8/00 , G11C11/408
CPC classification number: G11C8/08 , G11C11/4085
Abstract: The invention relates to a row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, being of the type adapted to boost, through at least one boost capacitor (Cboost), a read voltage to be applied to a memory column containing a memory cell to be read. The circuit is powered between a first supply voltage reference (Vpcx) and a second ground potential reference (GND), and comprises a hierarchic structure (13) of cascade connected inverters (15,16) and a circuit means of progressively raising the read voltage level dynamically. First means (Cboost0,D1) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus a threshold voltage (Vtp), and second means (Cboost1,D2) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus twice said threshold voltage (Vtp).
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89.发明公开Memory cell integrated structure and corresponding biasing device 失效Vorspannungsvorrichtungfürintegrierte Speicherzellenstruktur
公开(公告)号：EP0952615A1
公开(公告)日：1999-10-27
申请号：EP98830238.6
申请日：1998-04-22
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Zanardi, Stefano , Branchetti, Maurizio , Ghezzi, Stefano
IPC: H01L27/115 , G05F3/20
CPC classification number: H01L27/115 , G05F3/205
Abstract: The invention relates to an integrated structure (1) for memory cells formed over a semiconductor substrate (2) doped with a first dopant type and including at least one memory cell (CM) in turn formed in a conductive well (3) provided in said semiconductor substrate (2) and doped with a second dopant type, said conductive well (3) having an additional well (4) formed therein which is doped with the first dopant type and comprises active areas (5,6) of the memory cell (CM).
According to the invention, a substrate bias terminal (8), formed in the additional well (4), is further associated with the memory cell (CM) to receive a suitable bias voltage (Vpol) to lower the threshold voltage (Vth) of the memory cell (CM) by body effect.
The invention also relates to a biasing device (13) for a memory cell (CM) which has at least one substrate bias terminal (8) associated therewith, the biasing device comprising at least a first sub-threshold circuitry block (A) adapted to supply an appropriate current during the device standby phase through a restore transistor (M1) connected between a supply voltage reference (Vcc) and the substrate bias terminal (8) of the memory cell (CM), and having a control terminal connected to a bias circuit (14), in turn connected between the supply voltage reference (Vcc) and a ground voltage reference (GND) to drive the restore transistor (M1) with a current of limited value.
The device according to the invention further comprises a second feedback block (B) for fast charging the substrate bias terminal (8), being connected between the supply voltage reference (Vcc) and the ground voltage reference (GND) and comprising a first bias transistor (M2) having a control terminal connected to the ground voltage reference (GND) via a stabilization transistor (M3), having in turn a control terminal connected to an output node (OC), and to the control terminal of a first regulation transistor (M4) connected between the supply voltage reference (Vcc) and the ground voltage reference (GND), the stabilization transistor (M3) and first regulation transistor (M4) providing feedback for the bias transistor (M2), thereby to restrict the voltage range of the output node (OC).Abstract translation: 本发明涉及一种用于存储单元的集成结构（1），其形成于掺杂有第一掺杂剂类型的半导体衬底（2）上，并且还包括至少一个存储单元（CM），所述至少一个存储单元又形成在所述导电阱 半导体衬底（2）并掺杂有第二掺杂剂类型，所述导电阱（3）具有形成在其中的附加阱（4），其中掺杂有第一掺杂剂类型，并且包括存储器单元的有源区（5,6） 厘米）。 根据本发明，形成在附加阱（4）中的衬底偏置端子（8）还与存储单元（CM）相关联以接收合适的偏置电压（Vpol）以降低阈值电压（Vth） 记忆体（CM）通过身体效应。 本发明还涉及一种用于存储单元（CM）的偏置装置（13），其具有至少一个与其相关联的衬底偏置端子（8），所述偏置装置至少包括第一子阈值电路块（A） 在器件待机阶段通过连接在电源电压基准（Vcc）和存储单元（CM）的衬底偏置端子（8）之间的还原晶体管（M1）提供适当的电流，并且具有连接到偏置的控制端子 电路（14）又连接在电源电压基准（Vcc）和接地电压基准（GND）之间，以限制电流驱动恢复晶体管（M1）。 根据本发明的装置还包括用于对衬底偏置端子（8）进行快速充电的第二反馈块（B），其连接在电源电压参考（Vcc）和接地电压基准（GND）之间，并且包括第一偏置晶体管 （M2），其具有经由稳定晶体管（M3）连接到接地电压基准（GND）的控制端子，其具有连接到输出节点（OC）的控制端子和第一调节晶体管（...的控制端子） M4）连接在电源电压基准（Vcc）和接地电压基准（GND）之间，稳定晶体管（M3）和第一调节晶体管（M4）为偏置晶体管（M2）提供反馈，从而限制 输出节点（OC）。
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90.发明公开Data protection method for a semiconductor memory and corresponding protected memory device 失效一种用于半导体存储器件的数据备份的方法和相应的受保护的存储器装置
公开(公告)号：EP0926601A1
公开(公告)日：1999-06-30
申请号：EP97830717.1
申请日：1997-12-24
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Ghezzi, Stefano , Giannini, Giuseppe , Torricelli, Piero Enrico
CPC classification number: G07F7/1008 , G06F12/1433 , G06F21/79 , G06Q20/341 , G06Q20/357 , G11C8/20 , G11C16/22
Abstract: The invention relates to a method of protecting data in a semiconductor electronic memory comprising a memory matrix (2) and respective matrix address decoding (3) and predecoding (4) blocks. The method consists of using a protected memory portion (5) within said matrix (2) and respective dedicated decoding portions (6,7) for storing, into the protected portion (5), a protection code (CP) external to the address area of the matrix (2).
The protection code (CP) can only be written and/or read through a command interpreter (8).Abstract translation: 本发明涉及保护数据在半导体电子存储器包括存储器矩阵的方法（2）和相应的矩阵地址译码（3）和预解码（4）块。 所述基质内使用受保护的存储器部分（5）的方法，besteht（2）以及用于存储，进入外部的地址区中的受保护的部分（5），一个保护码（CP）各自专用的解码部（6,7） 矩阵的（2）。 保护代码（CP）只能通过一个命令解释器（8）被写入和/或读出。
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