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    Chip scale stacking system and method
    1.
    发明专利
    Chip scale stacking system and method 未知

    公开(公告)号：GB2395367A

    公开(公告)日：2004-05-19

    申请号：GB0406140

    申请日：2002-10-25

    Applicant: STAKTEK GROUP LP

    Inventor： CADY JAMES W ,  WILDER JAMES ,  ROPER DAVID L ,  WEHRLY JAMES DOUGLAS ,  DOWDEN JULIAN ,  BUCHLE JEFF

    IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/48 ,  H05K1/00

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module (10) devised in accordance with a preferred embodiment of the present invention, a pair of CSPs (12, 14) is stacked, with one CSP (12) above the other (14). The two CSPs are connected with a pair of flexible circuit structures (30, 32). Each of the pair of flexible circuit structures (30, 32) is partially wrapped about a respective opposite lateral edge (20, 22) of the lower CSP (14) of the module (10). The flex circuit pair (30, 32) connects the upper and lower CSPs (12, 14) and provides a thermal and electrical path connection path between the module (10) and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.

    Chip scale stacking system and method
    2.
    发明专利
    Chip scale stacking system and method 未知

    公开(公告)号：GB2395367B

    公开(公告)日：2005-05-25

    申请号：GB0406140

    申请日：2002-10-25

    Applicant: STAKTEK GROUP LP

    Inventor： CADY JAMES W ,  WILDER JAMES ,  ROPER DAVID L ,  WEHRLY JAMES DOUGLAS ,  DOWDEN JULIAN ,  BUCHLE JEFF

    IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/48 ,  H05K1/00

    Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

    MEMORY EXPANSION AND INTEGRATED CIRCUIT STACKING SYSTEM AND METHOD
    3.
    发明专利
    MEMORY EXPANSION AND INTEGRATED CIRCUIT STACKING SYSTEM AND METHOD 未知

    公开(公告)号：AU2003304192A1

    公开(公告)日：2005-01-04

    申请号：AU2003304192

    申请日：2003-09-15

    Applicant: STAKTEK GROUP LP

    Inventor： WEHRLY JAMES DOUGLAS JR ,  BUCHLE JEFF ,  RAPPORT RUSSELL ,  CADY JAMES W ,  WILDER JAMES ,  ROPER DAVID L

    IPC: H01L21/44 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.

    A HIGH-DENSITY CIRCUIT MODULE
    4.
    发明专利
    A HIGH-DENSITY CIRCUIT MODULE 未知

    公开(公告)号：HK1077460A1

    公开(公告)日：2006-02-10

    申请号：HK05109243

    申请日：2005-10-22

    Applicant: STAKTEK GROUP LP

    Inventor： CADY JAMES W ,  WILDER JAMES ,  ROPER DAVID L ,  WEHRLY JAMES DOUGLAS ,  DOWDEN JULIAN ,  BUCHLE JEFF

    IPC: H01L20090101 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

    Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

    STACKED MODULE SYSTEMS AND METHODS
    5.
    发明申请
    STACKED MODULE SYSTEMS AND METHODS 审中-公开
    堆叠模块系统和方法

    公开(公告)号：WO2007053523A3

    公开(公告)日：2007-10-04

    申请号：PCT/US2006042232

    申请日：2006-10-27

    Applicant: STAKTEK GROUP LP ,  PARTRIDGE JULIAN ,  WEHRLY JAMES DOUGLAS ,  ROPER DAVID L ,  VILLANI JOSEPH

    Inventor： PARTRIDGE JULIAN ,  WEHRLY JAMES DOUGLAS ,  ROPER DAVID L ,  VILLANI JOSEPH

    IPC: H01L23/52 ,  H01L25/065

    CPC classification number: H01L23/49833 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H05K3/305 ,  H05K2201/056 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2224/0401

    Abstract: The present invention stacks integrated circuit packages into circuit modules. In a preferred embodiment, solder paste and primary adhesive respectively are applied to selected locations on the flex circuitry. Supplemental adhesive is applied to add ional locations on the flex circuitry, CSP, or other component. The flex circuitry and the CSP are brought into proximity with each other. During solder reflow operation, a force is applied and the CSP collapses toward the flex circuitry, displacing the primary adhesive and the supplemental adhesive. The supplemental adhesive establishes a bond providing additional support to the flex circuitry. In another embodiment, CSPs or other integrated circuit packages are bonded to each other or to other components with a combination of adhesives. A rapid bond adhesive maintains alignment of the bonded packages and/or components during assembly, and a structural bond adhesive provides additional strength and/or structural integrity to the bond.

    Abstract translation: 本发明将集成电路封装堆叠到电路模块中。 在优选实施例中，分别将焊膏和主粘合剂施加到柔性电路上的选定位置。 补充粘合剂用于在柔性电路，CSP或其他组件上添加离子位置。 柔性电路和CSP彼此靠近。 在回流焊操作期间，施加力并且CSP朝柔性电路折叠，取代主粘合剂和辅助粘合剂。 补充粘合剂建立了为柔性电路提供额外支撑的粘合。 在另一个实施例中，CSP或其他集成电路封装通过粘合剂的组合彼此粘合或粘合到其他组件。 快速粘合粘合剂在组装期间保持粘合的封装和/或部件的对齐，并且结构粘合粘合剂为粘合提供额外的强度和/或结构完整性。

    THIN CIRCUIT MODULE AND METHOD
    6.
    发明申请
    THIN CIRCUIT MODULE AND METHOD 审中-公开
    薄膜电路模块和方法

    公开(公告)号：WO2009039263A3

    公开(公告)日：2009-10-15

    申请号：PCT/US2008076839

    申请日：2008-09-18

    Applicant: STAKTEK GROUP LP ,  WOLFE MARK ,  WILDER JAMES ,  ROPER DAVID L

    Inventor： WOLFE MARK ,  WILDER JAMES ,  ROPER DAVID L

    IPC: H01R12/16 ,  G06F12/00 ,  H01R13/10 ,  H01R13/62

    CPC classification number: H05K1/183 ,  H05K1/0203 ,  H05K1/117 ,  H05K2201/09972 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2203/1572 ,  Y10T29/49124

    Abstract: A circuit module includes a printed circuit board (PCB) (12) having a first side (22), a second side (24), and a bottom perimeter edge (42). The PCB exhibits a first thickness along the bottom perimeter edge. The first side includes a recessed area (70) and, in that recessed area, the PCB has a second thickness that is less than the first thickness. A plurality of integrated circuits (ICs) are fixed to the PCB in the recessed area. A plurality of module contacts (30) are connected to the ICs and are disposed along at least one of the first and second sides and are configured to provide electrical connection between the circuit module and an edge connector.

    Abstract translation: 电路模块包括具有第一侧面（22），第二侧面（24）和底部周边边缘（42）的印刷电路板（PCB）（12）。 PCB沿底部周边边缘呈现第一厚度。 第一侧包括凹入区域（70），并且在该凹入区域中，PCB具有小于第一厚度的第二厚度。 多个集成电路（IC）被固定到凹陷区域中的PCB。 多个模块触点（30）连接到IC并且沿着第一和第二侧中的至少一个设置，并且被配置为提供电路模块和边缘连接器之间的电连接。

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