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公开(公告)号：KR1020090004158A
公开(公告)日：2009-01-12
申请号：KR1020070068150
申请日：2007-07-06
Applicant: 삼성전자주식회사
Inventor： 김남빈
IPC: H01L27/115
CPC classification number: H01L45/143 , G11C13/0004 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L21/28141
Abstract: The phase change memory device and a method of forming the same are provided to minimize the leakage current of the selection element by using the selection element electrically connected with the phase change material pattern. The selection element(120) comprises the metallic conductor(116) and the contacted semiconductor(114a). The phase change material pattern(130) is electrically connected to the selection element. In the equilibrium state, the depletion region is generated between the semiconductor and metallic conductor. The depletion region comprises the low barrier region and the high barrier region. The high barrier region is arranged between the storage unit domain and metallic conductor.
Abstract translation: 提供相变存储器件及其形成方法，以通过使用与相变材料图案电连接的选择元件来最小化选择元件的漏电流。 选择元件（120）包括金属导体（116）和接触半导体（114a）。 相变材料图案（130）电连接到选择元件。 在平衡状态下，在半导体和金属导体之间产生耗尽区。 耗尽区包括低阻挡区和高阻挡区。 高阻挡区域布置在存储单元域和金属导体之间。
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公开(公告)号：KR1020080099423A
公开(公告)日：2008-11-13
申请号：KR1020070044949
申请日：2007-05-09
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/2463 , H01L21/31051 , H01L21/76897 , H01L27/10882
Abstract: The plane area(planar area) of the memory cell can be minimized and defects generated in burying metal in a contact hole having a big aspect rate can be prevented. The word line(WL2) having the first conductivity type and the other second conductive type is formed on the semiconductor substrate(100) of the first conductivity type. The laminated semiconductor patterns and the metal pattern which passes through the mold dielectric film are formed. The above semiconductor pattern(128) overlaps with the word line. The mold dielectric film(110) is formed on the semiconductor substrate having word line. The interlayer insulating film(150) is formed on the semiconductor substrate having metal pattern. The first electrode(160) which is electrically connected with the metal pattern is formed. The first electrode has the plane area which is smaller than that of the metal pattern. The intermetal insulator(177) is formed on the semiconductor substrate having the second electrode. The metal line(195) overlapping the word line on the intermetal insulator layer is formed.
Abstract translation: 可以使存储单元的平面面积（平面面积）最小化，能够防止在具有大的纵横比的接触孔中埋入金属时产生的缺陷。 具有第一导电类型和另一第二导电类型的字线（WL2）形成在第一导电类型的半导体衬底（100）上。 形成层叠的半导体图案和通过模具电介质膜的金属图案。 上述半导体图案（128）与字线重叠。 模具电介质膜（110）形成在具有字线的半导体衬底上。 层间绝缘膜（150）形成在具有金属图案的半导体衬底上。 形成与金属图案电连接的第一电极（160）。 第一电极具有小于金属图案的平面面积。 金属间绝缘体（177）形成在具有第二电极的半导体衬底上。 形成与金属间绝缘体层上的字线重叠的金属线（195）。
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公开(公告)号：KR1020160139119A
公开(公告)日：2016-12-07
申请号：KR1020150073117
申请日：2015-05-26
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11582 , H01L27/1157
Abstract: 본발명의반도체장치에관한것으로, 기판, 상기기판상에수직적으로적층된게이트전극들, 상기게이트전극들사이의절연패턴들, 상기게이트전극들과상기절연패턴들을관통하여상기기판과전기적으로연결되는활성기둥및 상기게이트전극들과상기활성기둥사이, 및상기절연패턴들과상기활성기둥사이에개재되는정보저장패턴을포함하고, 상기게이트전극들은, 상기정보저장패턴과상기절연패턴들사이에연장되는에지부들(edge portions)을포함하는반도체장치가제공된다.
Abstract translation: 本发明提供一种半导体器件，包括基板，垂直堆叠在基板上的栅电极，栅电极之间的绝缘图案，设置成穿过栅电极的活性柱和绝缘图案，并与基板电耦合，以及存储图案， 栅电极和有源支柱以及绝缘图案和有源支柱之间。 栅电极包括在存储器图案和绝缘图案之间延伸的边缘部分。
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公开(公告)号：KR101338160B1
公开(公告)日：2013-12-06
申请号：KR1020070068150
申请日：2007-07-06
Applicant: 삼성전자주식회사
Inventor： 김남빈
IPC: H01L27/115
CPC classification number: H01L45/143 , G11C13/0004 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1675
Abstract: 본 발명은 상변화 기억 소자 및 그 형성 방법을 제공한다. 이 소자에 따르면, 상변화 물질 패턴과 전기적으로 접속된 선택 소자는 서로 접속된 금속성 도체 및 반도체를 포함한다. 이때, 평형 상태에서 반도체에는 금속성 패턴과 접하는 공핍 영역이 생성된다. 공핍 영역은 계면 전위 장벽에 비하여 큰 전위 장벽을 갖는 고장벽 영역 및 계면 전위 장벽에 비하여 작은 전위 장벽을 갖는 저장벽 영역을 포함한다.
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