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公开(公告)号：KR101812593B1
公开(公告)日：2017-12-28
申请号：KR1020110134462
申请日：2011-12-14
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L21/823857 , H01L21/28185 , H01L21/3115 , H01L27/10876 , H01L27/10894 , H01L29/517 , H01L29/66545
Abstract: 반도체장치의제조방법이제공된다. 기판상에게이트절연막패턴을형성한다. 상기게이트절연막패턴상에불순물이도핑된희생층을형성한다. 상기희생층에도핑된불순물이상기게이트절연막패턴내로확산되도록어닐링공정을수행한다. 상기희생층을제거한다. 상기게이트절연막패턴상에게이트전극을형성한다. 상기반도체장치는우수한전기적특성을갖는다.
Abstract translation: 提供了一种制造半导体器件的方法。 由此在衬底上形成栅极绝缘膜图案。 在栅绝缘膜图案上形成掺杂有杂质的牺牲层。 执行退火处理以扩散到牺牲层中的掺杂移相器栅极绝缘膜图案中。 牺牲层被移除。 栅极电极形成在栅极绝缘膜图案上。 该半导体器件具有优异的电特性。
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公开(公告)号：KR1020120035701A
公开(公告)日：2012-04-16
申请号：KR1020100097388
申请日：2010-10-06
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7827 , H01L27/10876 , H01L27/228 , H01L27/2436 , H01L29/66666 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L29/4236
Abstract: PURPOSE: A semiconductor device and a formation method thereof are provided to prevent an electrical short of a liner electrode and contact plugs by increasing the distance between the liner electrode and the contact plug. CONSTITUTION: A bulk electrode(135) is arranged within a trench. A liner electrode(125) is formed between the bulk electrode and the inner surface of the trench. The liner electrode includes a sidewall part. The sidewall part is arranged between sidewalls of the bulk electrode and the trench. A gate dielectric film(110) is arranged between the inner surface of the trench and the liner electrode.
Abstract translation: 目的：提供半导体器件及其形成方法，以通过增加衬垫电极和接触插塞之间的距离来防止衬里电极和接触插塞的电短路。 构成：在沟槽内布置体电极（135）。 衬垫电极（125）形成在体电极和沟槽的内表面之间。 衬垫电极包括侧壁部分。 侧壁部分布置在体电极和沟槽的侧壁之间。 栅极介电膜（110）布置在沟槽的内表面和衬里电极之间。
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公开(公告)号：KR1020100026741A
公开(公告)日：2010-03-10
申请号：KR1020080085863
申请日：2008-09-01
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L27/10876 , H01L21/32134 , H01L21/823412 , H01L21/823437 , H01L21/823468
Abstract: PURPOSE: A method for manufacturing a semiconductor device including a recessed channel is provided to prevent a bridge between metal nitride and poly-silicon from generating by selectively etching a lower conductive layer. CONSTITUTION: A gate oxide layer(114) is conformally formed on a semiconductor substrate in which a trench(112a) is formed. A gate structure including the stacked structure of a lower conductive layer pattern(116a), a poly-silicon layer pattern(118a), an upper conductive layer pattern(126a) and a mask is formed. A capping layer is formed on the gate structure and the substrate. A capping layer spacer is formed on the sidewall of the gate structure. Impurities are implanted to the substrate to form a source/drain using the capping layer spacer and the gate structure as a ion-implantation mask.
Abstract translation: 目的：提供一种制造包括凹陷通道的半导体器件的方法，以通过选择性地蚀刻下导电层来防止金属氮化物和多晶硅之间的桥接产生。 构成：在形成有沟槽（112a）的半导体衬底上共形地形成栅氧化层（114）。 形成包括下导电层图案（116a），多晶硅层图案（118a），上导电层图案（126a）和掩模的层叠结构的栅极结构。 在栅极结构和衬底上形成覆盖层。 在栅极结构的侧壁上形成覆盖层间隔物。 将杂质植入衬底中以形成源极/漏极，使用覆盖层间隔物和栅极结构作为离子注入掩模。
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公开(公告)号：KR101749055B1
公开(公告)日：2017-06-20
申请号：KR1020100097388
申请日：2010-10-06
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7827 , H01L27/10876 , H01L27/228 , H01L27/2436 , H01L29/66666 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146
Abstract: 반도체장치및 그형성방법을제공한다. 본발명에따른반도체소자는기판내에배치된트렌치, 상기트렌치내에벌크전극, 상기벌크전극과상기트렌치의내면사이에라이너전극및 상기라이너전극과상기트렌치의내면사이에게이트유전막을포함할수 있다. 상기라이너전극은상기벌크전극의측벽및 상기트렌치의측벽사이에개재되는측벽부를포함할수 있고, 상기벌크전극의상부면의레벨은상기라이너전극의상기측벽부의상부면의레벨보다높고, 상기기판의상부면의레벨보다는낮을수 있다.
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公开(公告)号：KR101651941B1
公开(公告)日：2016-08-30
申请号：KR1020100013901
申请日：2010-02-16
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L27/10876 , H01L29/66628
Abstract: 실리콘리플로우공정을이용하여리세스채널용트렌치의프로파일이개선되는반도체소자의제조방법이제공된다. 반도체소자의제조방법은, 기판의활성영역의일부와소자분리영역의일부를리세스함으로써, 기판에소정깊이의리세스채널용트렌치가형성되고, 리세스채널용트렌치는하부폭이상부폭보다좁고, 상기기판을어닐링함으로써, 상기활성영역과접하는리세스채널용트렌치의프로파일에서바닥면의넓이가확장되고, 바닥면의레벨은리프트되며, 상기소자분리영역과접하는리세스채널용트렌치의프로파일에서바닥면의레벨은상기어닐링전과동일하게형성되는것으로구성될수 있다.
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Patent Agency Ranking
公开(公告)号：KR1020120039136A
公开(公告)日：2012-04-25
申请号：KR1020100100666
申请日：2010-10-15
Applicant: 삼성전자주식회사
IPC: H01L21/8238
Abstract: PURPOSE: A manufacturing method of a semiconductor device is provided to improve negative voltage temperature instability by eliminating the upper part of an auxiliary metal barrio film pattern. CONSTITUTION: A gate dielectric film pattern, an auxiliary metal barrier film pattern, a sacrificial gate, and a gate spacer are formed on a substrate. A source/drain region is formed on the substrate of both sides of the gate spacer. An insulating film pattern is formed with the height of the upper surface of the sacrificial gate. A metal barrier film pattern(136) is formed by eliminating the upper part of the auxiliary metal barrier film pattern after eliminating the sacrificial gate. A gate structure(222) which includes a metal film pattern, the metal barrier film pattern, and the gate dielectric film pattern are formed on a PMOS(P-channel Metal Oxide Semiconductor) region of the substrate.
Abstract translation: 目的：提供一种半导体器件的制造方法，通过消除辅助金属棒状膜图案的上部来改善负电压温度不稳定性。 构成：在基板上形成栅极电介质膜图案，辅助金属阻挡膜图案，牺牲栅极和栅极间隔物。 源极/漏极区域形成在栅极间隔物的两侧的衬底上。 以牺牲栅极的上表面的高度形成绝缘膜图案。 在消除牺牲栅极之后，通过消除辅助金属阻挡膜图案的上部来形成金属阻挡膜图案（136）。 在衬底的PMOS（P沟道金属氧化物半导体）区域上形成包括金属膜图案，金属阻挡膜图案和栅极电介质膜图案的栅极结构（222）。
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公开(公告)号：KR1020090076028A
公开(公告)日：2009-07-13
申请号：KR1020080001753
申请日：2008-01-07
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L29/66553 , H01L21/28079 , H01L21/28114 , H01L29/4236
Abstract: A semiconductor device and a manufacturing method thereof are provided, which improve turn on current value by providing the gate within the gate trench. The gate trench(112) within the substrate(110) has the side wall contacting with source and drain region(120). The gate insulating layer(130) is formed along the gate trench inner surface. The metal pattern(145) is formed at the lower part of the gate trench. The non-metal conductive pattern(155) is formed in the upper part of the metal pattern. The channel region within substrate faces the metal pattern and non-metal conductive pattern. The depth of the gate trench is deeper than the depth of the drain region and source.
Abstract translation: 提供一种半导体器件及其制造方法，其通过在栅极沟槽内提供栅极来提高导通电流值。 衬底（110）内的栅极沟槽（112）具有与源极和漏极区域（120）接触的侧壁。 栅极绝缘层（130）沿栅极沟槽内表面形成。 金属图案（145）形成在栅极沟槽的下部。 非金属导电图案（155）形成在金属图案的上部。 衬底内的沟道区域面向金属图案和非金属导电图案。 栅极沟槽的深度比漏极区域和源极的深度更深。
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公开(公告)号：KR101847630B1
公开(公告)日：2018-05-24
申请号：KR1020130035314
申请日：2013-04-01
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/4236 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L29/7827
Abstract: 반도체소자및 이를채택하는전자장치를제공한다. 이반도체소자는반도체기판의활성영역내에배치된제1 소스/드레인영역및 제2 소스/드레인영역을포함한다. 상기활성영역을가로지는게이트구조체가배치된다. 상기게이트구조체는상기제1 및제2 소스/드레인영역들사이에배치된다. 상기게이트구조체는제1 부분및 제1 부분상의제2 부분을가지며, 상기활성영역의상부면보다낮은레벨에배치된게이트전극; 상기게이트전극상의절연성캐핑패턴; 상기게이트전극과상기활성영역사이의게이트유전체; 및상기게이트전극의상기제2 부분과상기활성영역사이의빈 공간을포함한다.
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公开(公告)号：KR101374323B1
公开(公告)日：2014-03-17
申请号：KR1020080001753
申请日：2008-01-07
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L29/66553 , H01L21/28079 , H01L21/28114 , H01L29/4236
Abstract: 반도체 소자가 개시된다. 상기 소자는 기판 내의 게이트 트렌치 내에 내재된 하부 금속패턴 및 상기 하부 금속패턴 상의 비금속 도전패턴을 포함할 수 있다. 이로써, 우수한 전기적 특성을 갖는 반도체 소자가 제공될 수 있다.
채널, 게이트 트렌치, 턴온 전류, 문턱 전압, GIDL-
公开(公告)号：KR1020140016694A
公开(公告)日：2014-02-10
申请号：KR1020120083753
申请日：2012-07-31
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L27/092 , H01L21/823437 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857
Abstract: The present invention relates to a semiconductor device manufacturing method which forms a thin film on a substrate including a first region and a second region. A gate insulation film is formed on the thin film. A lower electrode film is formed on the gate insulation film. The gate insulation film is exposed at the second region by removing a part of the lower electrode film positioned at the second region. Nitrogen is injected to the part of the thin film positioned at the exposed gate thin film or under the same. An upper electrode film is formed at the lower electrode film remaining at the first region, and the exposed gate insulation film part. A first gate structure and a second gate structure are respectively formed at the first and second regions by partially removing the upper electrode film, the lower electrode film, the gate insulation film, and the thin film.
Abstract translation: 本发明涉及在包括第一区域和第二区域的基板上形成薄膜的半导体器件制造方法。 在薄膜上形成栅极绝缘膜。 在栅极绝缘膜上形成下部电极膜。 通过去除位于第二区域的下部电极膜的一部分，在第二区域露出栅极绝缘膜。 将氮气注入位于暴露的栅极薄膜处的薄膜的部分或其下方。 在保持在第一区域的下电极膜和暴露的栅绝缘膜部分上形成上电极膜。 通过部分去除上电极膜，下电极膜，栅极绝缘膜和薄膜，分别在第一和第二区域形成第一栅极结构和第二栅极结构。
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