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    박막 트랜지스터의 제조방법
    1.
    发明授权
    박막 트랜지스터의 제조방법 有权
    薄膜晶体管的制作方法

    公开(公告)号：KR100763913B1

    公开(公告)日：2007-10-05

    申请号：KR1020060038334

    申请日：2006-04-27

    Applicant: 삼성전자주식회사

    Inventor： 박재철 ,  박영수 ,  차영관

    IPC: H01L29/786

    CPC classification number: H01L27/12 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/66757 ,  H01L29/78618 ,  H01L27/1214 ,  H01L29/458

    Abstract: A method for manufacturing a TFT is provided to prevent the contamination of a metal electrode and to lessen the degradation of step coverage due to a stacked portion under a gate insulating layer. A silicon channel material layer and a silicon ohmic material layer are sequentially formed on a substrate(20). Source and drain ohmic layers(23s,23d) for contacting a silicon channel and both end portions of the silicon channel are formed on the resultant structure by patterning selectively the channel material layer and the ohmic material layer. A gate insulating layer(24) is formed on the resultant structure to cover the source and drain ohmic layers. A gate(25) is formed on the gate insulating layer corresponding to the channel. An interlayer dielectric(26) for covering the gate is formed on the gate insulating layer. A contact hole(H) through the interlayer dielectric and the gate insulating layer is formed on the source and drain ohmic layers, respectively. Source and drain electrodes(27s,27d) for contacting the source and drain ohmic layers through the contact hole is formed on the interlayer dielectric. A passivation layer is then formed on the resultant structure to cover the source and drain electrodes.

    Abstract translation: 提供一种用于制造TFT的方法，以防止金属电极的污染，并且减少由栅极绝缘层下方的层叠部分引起的阶梯覆盖的劣化。 在衬底（20）上依次形成硅沟道材料层和硅欧姆材料层。 通过对沟道材料层和欧姆材料层进行图案化，在所得结构上形成用于接触硅沟道和硅沟道的两个端部的源极和漏极欧姆层（23s，23d）。 在所得结构上形成栅极绝缘层（24）以覆盖源极和漏极欧姆层。 在对应于通道的栅极绝缘层上形成栅极（25）。 在栅极绝缘层上形成用于覆盖栅极的层间电介质（26）。 在源极和漏极欧姆层上分别形成穿过层间电介质和栅极绝缘层的接触孔（H）。 用于通过接触孔接触源极和漏极欧姆层的源极和漏极（27s，27d）形成在层间电介质上。 然后在所得结构上形成钝化层以覆盖源电极和漏电极。

    메모리 소자의 프로그램 및 소거 방법
    2.
    发明公开
    메모리 소자의 프로그램 및 소거 방법 失效
    存储器件的程序和擦除方法

    公开(公告)号：KR1020070092915A

    公开(公告)日：2007-09-14

    申请号：KR1020060022895

    申请日：2006-03-11

    Applicant: 삼성전자주식회사

    Inventor： 박상진 ,  박영수 ,  신상민 ,  차영관

    IPC: G11C16/10 ,  G11C16/14

    CPC classification number: G11C16/0416 ,  B82Y10/00 ,  G11C2216/06 ,  H01L29/42332 ,  H01L29/7881

    Abstract: A method of programming and erasing a memory device is provided to accelerate program speed rather than erase speed by applying a negative voltage to the memory device during a program operation and applying a positive voltage to the memory device during an erase operation. According to a method of programming and erasing a memory device including a substrate and a gate structure formed on the substrate, the gate structure of the memory device is characterized in that a flat band voltage is shifted faster in a negative voltage bias than in a positive voltage bias. The negative voltage bias is applied to the memory device during a program operation and the positive voltage bias is applied to the memory device during an erase operation. The gate structure comprises a charge trap layer formed with one of silicon rich oxide and silicon nano crystal.

    Abstract translation: 提供了一种编程和擦除存储器件的方法，用于通过在编程操作期间向存储器件施加负电压并且在擦除操作期间向存储器件施加正电压来加速编程速度而不是擦除速度。 根据一种编程和擦除包括形成在衬底上的衬底和栅极结构的存储器件的方法，存储器件的栅极结构的特征在于，平坦带电压在负电压偏置中比正的偏移更快地偏移 电压偏置。 在编程操作期间将负电压偏压施加到存储器件，并且在擦除操作期间将正电压偏压施加到存储器件。 栅极结构包括由富硅氧化物和硅纳米晶体之一形成的电荷阱层。

    나노닷을 전하 트랩 사이트로 이용하는 전하 트랩형 메모리소자
    4.
    发明公开
    나노닷을 전하 트랩 사이트로 이용하는 전하 트랩형 메모리소자 失效
    使用NANODOT作为电荷捕捉站的充电陷阱存储器件

    公开(公告)号：KR1020080056590A

    公开(公告)日：2008-06-23

    申请号：KR1020060129679

    申请日：2006-12-18

    Applicant: 삼성전자주식회사

    Inventor： 최상무 ,  차영관 ,  설광수 ,  박상진 ,  신상민 ,  박주희

    IPC: H01L27/115

    CPC classification number: H01L29/513 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/785 ,  H01L21/28282 ,  H01L29/4234

    Abstract: A charge trap memory device using a nano dot as a charge trap site is provided to simultaneously improve a write-read characteristic and a charge retention characteristic by solving a thermal stability problem of a memory device including a conventional pure metal nano dot. A charge trap memory device(10) includes a gate structure(20) on a substrate(11). In the gate structure, a plurality of metal oxide nano dots are discontinuously disposed as a charge trap site. The gate structure can include a tunneling insulation layer(21), the metal oxide nano dot(23) formed on the tunneling insulation layer, a blocking insulation layer(25) formed on the metal oxide nano dot, and a gate electrode(27) formed on the blocking insulation layer. First and second impurity regions(13,15) can be formed on the substrate to come in contact with the tunneling insulation layer.

    Abstract translation: 提供了使用纳米点作为电荷陷阱位置的电荷陷阱存储器件，以通过解决包括常规纯金属纳米点的存储器件的热稳定性问题来同时提高写入读取特性和电荷保持特性。 电荷陷阱存储器件（10）包括在衬底（11）上的栅极结构（20）。 在栅极结构中，多个金属氧化物纳米点被不连续地设置为电荷陷阱位置。 栅极结构可以包括隧道绝缘层（21），形成在隧道绝缘层上的金属氧化物纳米点（23），形成在金属氧化物纳米点上的阻挡绝缘层（25）和栅电极（27） 形成在隔离层上。 第一和第二杂质区（13,15）可以形成在衬底上以与隧道绝缘层接触。

    ＡＬＤ 공정에 의한 비정질 ＮｉＯ 박막의 제조방법 및상기 비정질 ＮｉＯ 박막을 이용한 비휘발성 메모리 소자
    6.
    发明公开
    ＡＬＤ 공정에 의한 비정질 ＮｉＯ 박막의 제조방법 및상기 비정질 ＮｉＯ 박막을 이용한 비휘발성 메모리 소자 有权
    ALD工作场所NiO工作场所및상기비정질NiO을을이용한비휘발성메모리소자

    公开(公告)号：KR1020070033743A

    公开(公告)日：2007-03-27

    申请号：KR1020050088236

    申请日：2005-09-22

    Applicant: 삼성전자주식회사

    Inventor： 박성호 ,  서범석 ,  이명재 ,  구준모 ,  서순애 ,  차영관

    IPC: H01L21/205 ,  H01L27/10

    CPC classification number: H01L27/115 ,  C23C16/406 ,  C23C16/45553 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

    Abstract: Example embodiments relate to a method of manufacturing amorphous NiO thin films and nonvolatile memory devices including amorphous thin films that use a resistance material. Other example embodiments relate to a method of manufacturing amorphous NiO thin films having improved switching and resistance characteristics by reducing a leakage current and non-volatile memory devices using an amorphous NiO thin film. Provided is a method of manufacturing an amorphous NiO thin film having improved switching behavior by reducing leakage current and improving resistance characteristics. The method may include preparing a substrate in a vacuum chamber, preparing a nickel precursor material, preparing a source gas by vaporizing the nickel precursor material, preparing a reaction gas, preparing a purge gas and forming a monolayer NiO thin film on the substrate by performing one cycle of sequentially supplying the source gas, the purge gas, the reaction gas and the purge gas into the vacuum chamber.

    Abstract translation: 示例实施例涉及制造非晶NiO薄膜的方法和包括使用电阻材料的非晶薄膜的非易失性存储器件。 其他示例实施例涉及通过减少泄漏电流来制造具有改进的开关和电阻特性的非晶NiO薄膜的方法以及使用非晶NiO薄膜的非易失性存储器件。 提供一种通过减少漏电流和改善电阻特性来制造具有改善的开关特性的非晶NiO薄膜的方法。 该方法可以包括：在真空室中制备衬底，制备镍前体材料，通过蒸发镍前体材料来制备源气体，制备反应气体，制备吹扫气体，并且通过执行在衬底上形成单层NiO薄膜 将源气体，净化气体，反应气体和净化气体依次供应到真空室中的一个循环。

    하부 게이트 박막 트랜지스터 및 그 제조방법
    9.
    发明授权
    하부 게이트 박막 트랜지스터 및 그 제조방법 失效
    底部薄膜薄膜晶体管及其制造方法

    公开(公告)号：KR100785020B1

    公开(公告)日：2007-12-12

    申请号：KR1020060052101

    申请日：2006-06-09

    Applicant: 삼성전자주식회사

    Inventor： 임혁 ,  박영수 ,  선우문욱 ,  차영관

    IPC: H01L29/786

    CPC classification number: H01L29/78678 ,  H01L21/268 ,  H01L27/1285 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696 ,  H01L21/02675

    Abstract: A bottom gate thin film transistor and a method for manufacturing the same are provided to improve the field effect mobility characteristic thereof by forming a lateral grown polycrystalline channel region. A bottom gate electrode(12) is formed on a substrate(10). A gate insulating layer(14) is formed on the substrate in order to cover the bottom gate electrode. An amorphous semiconductor layer, an N type semiconductor layer, and an electrode layer are sequentially formed on the gate insulating layer. A part of the amorphous semiconductor layer is exposed by etching sequentially a part of the electrode layer and a part of the N type semiconductor layer positioned on the gate electrode. The exposed amorphous semiconductor layer is molten by performing a laser annealing process. A lateral grown polycrystalline channel region is formed by crystallizing the molten amorphous channel region.

    Abstract translation: 提供底栅薄膜晶体管及其制造方法，通过形成横向生长的多晶沟道区域来提高其场效应迁移率特性。 底栅电极（12）形成在基板（10）上。 为了覆盖底栅电极，在基板上形成栅极绝缘层（14）。 在栅极绝缘层上依次形成非晶半导体层，N型半导体层和电极层。 通过依次蚀刻电极层的一部分和位于栅极上的N型半导体层的一部分来暴露非晶半导体层的一部分。 暴露的非晶半导体层通过进行激光退火处理而熔融。 通过使熔融的无定形沟道区域结晶来形成横向生长的多晶沟道区域。

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