公开(公告)号：KR1020130025204A

公开(公告)日：2013-03-11

申请号：KR1020110088583

申请日：2011-09-01

Applicant: 삼성전자주식회사

Inventor： 김대웅 ,  양준규 ,  김홍석 ,  한태종

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/764 ,  H01L21/28141 ,  H01L21/3213

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to minimize interference between adjacent cells by reducing a coupling effect between the adjacent cells. CONSTITUTION: A device isolation structure(20) is arranged on the substrate and defines an active region and includes a bottom insulation pattern(11a), a top insulation pattern(21a), and a gap region(17). The gap region is located between the bottom insulation pattern and the top insulation pattern. The bottom insulation pattern includes a silicon oxide layer. The top insulation pattern includes a buried insulation recess pattern and a spacer recess pattern(15c) arranged on both sidewalls of the buried insulation recess pattern.

Abstract translation: 目的：提供一种半导体器件及其制造方法，以通过减少相邻单元之间的耦合效应来最小化相邻单元之间的干扰。 构成：器件隔离结构（20）布置在衬底上并且限定有源区，并且包括底部绝缘图案（11a），顶部绝缘图案（21a）和间隙区域（17）。 间隙区域位于底部绝缘图案和顶部绝缘图案之间。 底部绝缘图案包括氧化硅层。 顶部绝缘图案包括埋置绝缘凹槽图案和布置在掩埋绝缘凹槽图案的两个侧壁上的间隔凹槽图案（15c）。

公开(公告)号：KR1020100035000A

公开(公告)日：2010-04-02

申请号：KR1020080094274

申请日：2008-09-25

Applicant: 삼성전자주식회사

Inventor： 한태종 ,  김문준 ,  정덕영 ,  백은경 ,  구주선

IPC: H01L21/76

CPC classification number: H01L21/76229

Abstract: PURPOSE: A different oxidation film for separating element is formed within the trenches having the element isolation trench gap fill method for having and semiconductor device using the same is the different aspect ratio. The generation of the void at the element isolation film or the core is prevented. CONSTITUTION: An element isolating trenches having aspect ratios different in the cell region of the semiconductor substrate(100) is formed. The oxide film is formed within element isolating trenches. Nitride liners are formed on oxide films. Nitride liners are thermally oxidized and the nitrate thermal oxide film(130) is formed. Element isolating trenches of the big aspect ratio are filled with nitrate thermal oxide films.

Abstract translation: 目的：在具有元件隔离沟槽间隙填充方法的沟槽内形成用于分离元件的不同氧化膜，并且使用其的半导体器件是不同的纵横比。 防止在元件隔离膜或芯部产生空隙。 构成：形成具有在半导体衬底（100）的单元区域中具有不同宽高比的沟槽的元件。 氧化膜形成在元件隔离槽内。 在氧化膜上形成氮化物衬垫。 氮化物衬垫被热氧化并形成硝酸盐热氧化膜（130）。 元素隔离大纵横比的沟槽填充有硝酸盐热氧化膜。

公开(公告)号：KR101807254B1

公开(公告)日：2018-01-11

申请号：KR1020110041112

申请日：2011-04-29

Applicant: 삼성전자주식회사

Inventor： 한태종 ,  김대웅 ,  장경태 ,  김봉철 ,  권오철

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L29/7926

Abstract: 반도체기억소자의형성방법이제공된다. 본발명에따른반도체기억소자의형성방법은기판상에제1 유전막들및 제1 물질막들을교대로그리고반복적으로형성하는것에의해서제1 적층구조체를형성하는것, 상기제1 적층구조체를관통하는제1 개구부를형성하는것, 상기제1 개구부내에차례로적층된벌크희생패턴및 캐핑희생패턴을형성하되, 상기벌크희생패턴은탄소를포함하는고분자화합물을포함하는것, 상기제1 적층구조체상에제2 유전막들및 제2 물질막들을교대로그리고반복적으로형성하는것에의해서제2 적층구조체를형성하는것, 상기제2 적층구조체를관통하여상기캐핑희생패턴을노출시키는제2 개구부를형성하는것 및상기캐핑희생패턴및 상기벌크희생패턴을제거하는것을포함할수 있다.

公开(公告)号：KR102007274B1

公开(公告)日：2019-08-05

申请号：KR1020130004193

申请日：2013-01-15

Applicant: 삼성전자주식회사

Inventor： 장경태 ,  이상훈 ,  서지연 ,  고현용 ,  남궁현 ,  김주완 ,  신승목 ,  이명범 ,  임지운 ,  한태종

IPC: H01L21/8247 ,  H01L27/115

公开(公告)号：KR1020160098658A

公开(公告)日：2016-08-19

申请号：KR1020150020259

申请日：2015-02-10

Applicant: 삼성전자주식회사

Inventor： 임지운 ,  박광철 ,  서지연 ,  이종명 ,  장경태 ,  전병호 ,  정원석 ,  최종완 ,  한태종

IPC: H01L27/115 ,  H01L21/31

CPC classification number: H01L27/11582 ,  H01L21/76837 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11521 ,  H01L21/31

Abstract: 본발명에따른반도체소자의제조방법은기판상에배치되며, 계단식구조를가지는적층구조체를형성하고, 상기적층구조체를덮으며, 제1 상면, 상기제1 상면보다높은레벨에위치한제2 상면, 및상기제1 상면과상기제2 상면을잇는경사면으로구성된적어도하나의계단부를포함하는제1 층간절연막을형성하고, 그리고상기제1 층간절연막을덮는제2 층간절연막을형성하는것을포함할수 있다. 상기제1 상면과상기경사면이이루는각도는제1 각도로정의되고, 상기제1 각도는둔각일수 있다.

Abstract translation: 根据本发明的制造半导体器件的方法包括：形成设置在基板上并具有阶梯结构的层状结构; 形成覆盖所述层叠结构的第一层间绝缘膜，并且包括第一上表面，位于比所述第一上表面高的位置的第二上表面，以及至少一个台阶部，所述至少一个台阶部包括将所述第一上表面 表面到第二上表面; 以及形成覆盖所述第一层间绝缘膜的第二层间绝缘膜。 第一上表面和倾斜表面之间的角度被定义为第一角度，其中第一角度可以是钝角。

公开(公告)号：KR1020140092015A

公开(公告)日：2014-07-23

申请号：KR1020130004193

申请日：2013-01-15

Applicant: 삼성전자주식회사

Inventor： 장경태 ,  이상훈 ,  서지연 ,  고현용 ,  남궁현 ,  김주완 ,  신승목 ,  이명범 ,  임지운 ,  한태종

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/1157 ,  H01L21/76877 ,  H01L21/823487 ,  H01L27/11578 ,  H01L29/7926

Abstract: In a method of manufacturing a vertical memory device, insulation films and sacrificial films are alternately and repeatedly formed on a substrate. A hole which exposes the upper surface of the substrate is formed by partially removing the insulation film and the sacrificial film. A semiconductor pattern which partially fills the partially expanded hole is formed on the upper surface of the substrate. A blocking film, a charging storage film, and a tunnel insulation film are sequentially formed on an inner wall of the hole and the semiconductor pattern. The upper surface of the semiconductor pattern is exposed by partially removing the tunnel insulation film, the charge storage film, and the blocking film. A channel is formed on the exposed semiconductor film and the tunnel insulation film. A gate electrode which replaces the sacrificial film is formed.

Abstract translation: 在制造垂直存储器件的方法中，绝缘膜和牺牲膜在衬底上交替地和重复地形成。 通过部分去除绝缘膜和牺牲膜来形成暴露基板的上表面的孔。 部分填充部分膨胀的孔的半导体图案形成在基板的上表面上。 在孔的内壁和半导体图案上依次形成阻挡膜，充电保存膜和隧道绝缘膜。 通过部分去除隧道绝缘膜，电荷存储膜和阻挡膜来暴露半导体图案的上表面。 在暴露的半导体膜和隧道绝缘膜上形成沟道。 形成代替牺牲膜的栅电极。

公开(公告)号：KR1020120122764A

公开(公告)日：2012-11-07

申请号：KR1020110041112

申请日：2011-04-29

Applicant: 삼성전자주식회사

Inventor： 한태종 ,  김대웅 ,  장경태 ,  김봉철 ,  권오철

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L29/7926 ,  H01L21/76205 ,  H01L21/76829 ,  H01L21/823487

Abstract: PURPOSE: A method for forming a semiconductor memory device is provided to minimize damage to first and second dielectric layers and first and second material layers by removing a bulk sacrificial pattern including polymer materials with carbon. CONSTITUTION: A first laminate structure(110) is formed by alternatively forming first dielectric layers and first material layers on a substrate. A first opening part(115) passing through the first laminate structure is formed. A bulk sacrificial pattern(123) and a capping sacrificial pattern(127) are successively laminated in the first opening part. A second laminate structure is formed by alternatively forming second dielectric layers and second material layers on the first laminate structure. A second opening part(135) is formed to expose the capping sacrificial pattern via the second laminate structure. The capping sacrificial pattern and the bulk sacrificial pattern are removed.

Abstract translation: 目的：提供一种用于形成半导体存储器件的方法，通过去除包括具有碳的聚合物材料的体牺牲图案来最小化对第一和第二介电层以及第一和第二材料层的损伤。 构成：通过在衬底上交替形成第一介电层和第一材料层来形成第一层压结构（110）。 形成穿过第一层压结构的第一开口部（115）。 在第一开口部分中依次层叠体牺牲图案（123）和封盖牺牲图案（127）。 通过在第一层压结构上交替地形成第二介电层和第二材料层来形成第二层压结构。 形成第二开口部分（135）以经由第二层压结构暴露封盖牺牲图案。 去除封盖牺牲图案和大量牺牲图案。

公开(公告)号：KR1020100102982A

公开(公告)日：2010-09-27

申请号：KR1020090021321

申请日：2009-03-12

Applicant: 삼성전자주식회사

Inventor： 최종완 ,  홍은기 ,  이보영 ,  한태종 ,  구주선 ,  변경문

IPC: H01L21/8247

CPC classification number: H01L29/7881 ,  H01L21/76229 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/11568 ,  H01L29/0649

Abstract: PURPOSE: A semiconductor device is provided to improve channel boosting efficiency during a program process and to improve the distribution of a channel voltage when a boost process is executed. CONSTITUTION: A tunnel insulating layer(310) and a charge trapping layer(320) are sequentially laminated on a substrate. A recess region(200) passes through a part of the charge trapping layer and the tunnel insulating layer and is defined with the side which is connected to a bottom surface. A first insulating pattern(230) has a distance between the inner walls which is a second width which is less than a first width.

Abstract translation: 目的：提供半导体器件，以在程序进程期间提高通道提升效率，并且在执行升压处理时改善通道电压的分布。 构成：隧道绝缘层（310）和电荷捕获层（320）依次层压在基板上。 凹陷区域（200）穿过电荷捕获层和隧道绝缘层的一部分，并且与连接到底表面的一侧限定。 第一绝缘图案（230）具有内壁之间的距离，第二宽度小于第一宽度。