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1.发明授权경사진 측벽을 갖는 활성 필라를 구비하는 비휘발성 메모리트랜지스터, 이를 구비하는 비휘발성 메모리 어레이 및상기 비휘발성 메모리 트랜지스터의 제조방법 有权非易失性存储器晶体管，包括具有斜面的活动支柱，具有晶体管的非易失性存储器阵列，以及制造晶体管的方法
公开(公告)号：KR100855992B1
公开(公告)日：2008-09-02
申请号：KR1020070032517
申请日：2007-04-02
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
IPC: H01L27/115
CPC classification number: H01L21/28282 , H01L21/28132 , H01L27/115 , H01L27/11568 , H01L29/1037 , H01L29/42332 , H01L29/42348 , H01L29/66787 , H01L29/7887 , H01L29/7923 , H01L29/7926 , H01L27/2463
Abstract: A non-volatile memory transistor including an active pillar having a sloped sidewall, a non-volatile memory array having the same, and a method for fabricating the same are provided to reduce power consumption by improving program efficiency. An active pillar(P) is protruded from a semiconductor substrate(10). The active pillar includes a sloped sidewall formed continuously from a surface of the semiconductor substrate. A gate electrode is formed to surround the sloped sidewall of the active pillar. An electric charge storage layer(23) is inserted between the active pillar and the gate electrode. A drain region(10d) is formed in an inside of an upper region of the active pillar. A source region(10s) is formed in the inside of the semiconductor substrate adjacent to a lower region of the active pillar.
Abstract translation: 提供了包括具有倾斜侧壁的有源支柱，具有其的非易失性存储器阵列及其制造方法的非易失性存储器晶体管，以通过提高程序效率来降低功耗。 活性柱（P）从半导体衬底（10）突出。 活性柱包括从半导体衬底的表面连续形成的倾斜侧壁。 栅电极形成为围绕有源支柱的倾斜侧壁。 电荷存储层（23）插入有源柱和栅电极之间。 漏极区域（10d）形成在有源支柱的上部区域的内部。 源极区域（10s）形成在与活性柱的下部区域相邻的半导体衬底的内部。
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公开(公告)号：KR1020080034685A
公开(公告)日：2008-04-22
申请号：KR1020060100947
申请日：2006-10-17
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/792 , H01L29/66833 , H01L29/7926 , H01L21/28282 , H01L21/31144
Abstract: An NVM(non-volatile memory) device is provided to improve electron injection efficiency by making the injection direction of electrons passing through the bottom surface of a charge trap layer have the transfer direction of electrons. A semiconductor substrate(104) includes a bottom part(104c) and a vertical part vertically protruding from the bottom part. The vertical part includes first and second vertical parts(104a,104b). A first vertical part is positioned in the upper part of the semiconductor substrate with respect to a boundary step. The second vertical part is positioned under the first vertical part, greater in width than the first vertical part and protruding to the outside of the first vertical part. A charge trap layer(134) is positioned outside the first vertical part and on the boundary step. A control gate electrode(150) is positioned on the bottom part and outside the second vertical part and the charge trap layer. A first insulation layer(124) can be interposed between the semiconductor substrate and the charge trap layer. A second insulation layer(144) can be interposed between the semiconductor substrate and the control gate electrode.
Abstract translation: 提供NVM（非易失性存储器）器件以通过使通过电荷陷阱层的底表面的电子的注入方向具有电子的传输方向来提高电子注入效率。 半导体衬底（104）包括底部（104c）和从底部垂直突出的垂直部分。 垂直部分包括第一和第二垂直部分（104a，104b）。 相对于边界步骤，第一垂直部分位于半导体衬底的上部。 第二垂直部分位于第一垂直部分下方，宽度大于第一垂直部分并且突出到第一垂直部分的外侧。 电荷捕获层（134）位于第一垂直部分的外侧和边界台阶上。 控制栅电极（150）位于第二垂直部分和电荷陷阱层的底部和外部。 第一绝缘层（124）可以插入在半导体衬底和电荷陷阱层之间。 可以在半导体衬底和控制栅电极之间插入第二绝缘层（144）。
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公开(公告)号：KR100889361B1
公开(公告)日：2009-03-18
申请号：KR1020060100947
申请日：2006-10-17
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/792 , H01L29/66833 , H01L29/7926
Abstract: 전자 주입 효율이 증가하고, 고집적도에 유리한 메모리 소자 및 이의 제조 방법이 제공된다. 메모리 소자는 바닥부, 및 바닥부로부터 수직하게 돌출되어 있는 수직부를 포함하되, 수직부는 경계단을 중심으로 상부에 위치하는 제1 수직부, 및 하부에 위치하며, 제1 수직부보다 폭이 크고, 제1 수직부의 외측으로 돌출되어 있는 제2 수직부를 포함하는 반도체 기판, 제1 수직부의 외측 및 경계단의 상부에 위치하는 전하 트랩층, 및 바닥부의 상부 및 제2 수직부와 전하 트랩층의 외측에 위치하는 컨트롤 게이트 전극을 포함한다.
플래쉬 메모리 소자, 수직부, 전자 주입 효율, 자기 정렬-
公开(公告)号：KR101692362B1
公开(公告)日：2017-01-05
申请号：KR1020110060773
申请日：2011-06-22
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/4958 , H01L21/82345 , H01L21/823828 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L27/0928 , H01L29/517 , H01L29/66545 , H01L29/78
Abstract: 식각정지절연막을이용한반도체장치의제조방법이제공된다. 반도체장치제조방법은, 제1 및제2 영역이정의된기판을제공하고, 상기제1 및제2 영역에각각형성된제1 및제2 트렌치를포함하는층간절연막을형성하고, 상기층간절연막의상면, 상기제1 트렌치의측면및 바닥면, 상기제2 트렌치의측면및 바닥면을따라서, 게이트절연막을컨포말하게형성하고, 상기게이트절연막상에식각정지절연막을형성하고, 상기제1 및제2 트렌치를매립하도록제1 금속막을형성하고, 상기식각정지절연막을식각정지막으로이용하여, 상기제1 영역의상기제1 금속막을제거하는것을포함한다.
Abstract translation: 制造半导体的方法可以包括提供其中限定有第一和第二区域的基板，分别形成层间电介质层，该层间绝缘层包括分别形成在第一和第二区域中的第一和第二沟槽，并沿着顶表面保形地形成栅介电层 层间介质层，第一沟槽和侧面的侧表面和底表面以及第二沟槽的底表面。 可以在栅极介电层上形成蚀刻停止介电层，可以形成第一金属层以填充第一和第二沟槽，并且可以使用蚀刻停止介电层作为蚀刻来去除第一区域中的第一金属层 塞子。
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公开(公告)号：KR101398666B1
公开(公告)日：2014-05-28
申请号：KR1020070123002
申请日：2007-11-29
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
Abstract: 본 발명은 플래시 메모리 장치를 제공한다. 상기 장치는 제 1 도전형을 갖는 반도체 기판으로부터 돌출되어 일 방향으로 연장되는 반도체 핀, 상기 반도체 핀의 상부(upper portion) 및 상기 반도체 핀의 하부(lower portion)에 각각 제공되어 서로 수직으로 이격된 제 2 도전형의 제 1 도핑층 및 제 2 도핑층, 및 상기 일 방향과 교차하도록 상기 반도체 핀의 표면 상으로 연장하는 복수의 워드 라인들을 포함한다. 상기 반도체 핀과 상기 워드 라인들 사이에 터널 절연막, 전하저장막 및 블로킹 절연막이 개재한다. 상기 복수개의 워드 라인들은 상기 제 1 도핑층 및 상기 제 2 도핑층과 중첩되어, 상기 플래시 메모리 장치를 수직 채널을 갖도록 한다.
수직 채널, 반도체 핀, 플래시, 집적도, 셀프 부스팅-
Patent Agency Ranking
公开(公告)号：KR1020110020398A
公开(公告)日：2011-03-03
申请号：KR1020090077996
申请日：2009-08-24
Applicant: 삼성전자주식회사
CPC classification number: H04W36/02
Abstract: PURPOSE: An apparatus and a method for handover optimization in a broadband wireless communication system are provided to adjust the timing of handover by judging the wrong handover and the occurrence of an RLF(Radio Link Failure) in a broadband wireless communication system. CONSTITUTION: A method for handover optimization in a broadband wireless communication system comprises the steps of: judging whether or not one of plural time intervals exceeds a critical time due to handover(301-305); deciding whether to move up or delay the timing of handover depending on the time interval which exceeds the critical time(306); changing a handover parameter to move up or delay the timing of handover(315); and using the history of the handover to judge whether or not an RLF(Radio Link Failure) results from the delay or the moving-up of the timing of the handover(317).
Abstract translation: 目的：提供宽带无线通信系统中切换优化的装置和方法，通过判断宽带无线通信系统中的错误切换和RLF（无线链路故障）的发生来调整切换定时。 一种宽带无线通信系统中的切换优化方法，包括以下步骤：判断多个时间间隔中的一个是否超过切换时间的关键时刻（301-305）; 根据超过临界时间的时间间隔决定是否向上移动或延迟切换的定时（306）; 改变切换参数以向上移动或延迟切换的定时（315）; 以及使用切换历史来判断RLF（无线链路失败）是否由切换的定时的延迟或上移导致（317）。
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公开(公告)号：KR1020110011145A
公开(公告)日：2011-02-08
申请号：KR1020090068656
申请日：2009-07-28
Applicant: 삼성전자주식회사
CPC classification number: H04W36/0083 , H04W36/14 , H04W36/24 , H04W36/0061 , H04W36/06
Abstract: PURPOSE: A method for optimizing an ANR configuration in a mobile communication system for efficiently using Inter-RAT/frequency cells in a base station is provided to optimize an ANR(Automatic Neighbor Relation) by adding, deleting and ranking the NR in the Inter-RAT/frequency cells. CONSTITUTION: A base station determines an adjacent cell reported from a terminal to an ON(Overlay Neighbor). The signal qualification of a serving cell(310) is bigger than a first reference value. The adjacent cell reported from a terminal is determined as an HN(Horizontal Neighbor). The signal qualification of the serving cell is smaller than a second reference value. The second reference value is set as the value smaller than the first reference value.
Abstract translation: 目的：提供一种用于优化移动通信系统中ANR配置的方法，用于有效地使用基站中的RAT间/频率小区，以通过在Inter-RAT /频率小区中添加，删除和排列NR来优化ANR（自动邻居关系） RAT /频率单元。 构成：基站确定从终端向ON（覆盖邻居）报告的相邻小区。 服务小区（310）的信号限定大于第一参考值。 从终端报告的相邻小区被确定为HN（水平邻居）。 服务小区的信号限定小于第二参考值。 将第二参考值设置为小于第一参考值的值。
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公开(公告)号：KR1020100111165A
公开(公告)日：2010-10-14
申请号：KR1020090029590
申请日：2009-04-06
Applicant: 삼성전자주식회사
IPC: H01L21/8229
CPC classification number: H01L27/1021 , G11C13/0004 , G11C2213/71 , H01L27/101
Abstract: PURPOSE: A 3D memory device is provided so that the manufacturing cost can be reduced in comparison with the other 3D memory device formed into the multilayer. CONSTITUTION: A 3D memory device comprises the semiconductor substrate(100), the insulating layer(150) between the plane word line(160) and the gate, activity post(180), and information storage film(170) is included. The semiconductor substrate comprises the common source area. The insulating layer is by turns laminated between plane word lines and gate on the semiconductor substrate.
Abstract translation: 目的：提供3D存储器件，以便与形成为多层的其它3D存储器件相比，可以减少制造成本。 构成：包括半导体衬底（100），平面字线（160）和栅极之间的绝缘层（150），活动柱（180）和信息存储膜（170）的3D存储器件。 半导体衬底包括公共源极区域。 绝缘层依次层叠在半导体衬底上的平面字线和栅极之间。
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公开(公告)号：KR1020100028723A
公开(公告)日：2010-03-15
申请号：KR1020080087580
申请日：2008-09-05
Applicant: 삼성전자주식회사
IPC: H04B7/26
CPC classification number: H04B7/026 , H04B7/15592 , H04W4/90
Abstract: PURPOSE: An apparatus and a method for transmitting emergency call in wireless cellular communication system, capable of increasing detection rate of help signal offer the efficient emergency call transmission strategy of a terminal capable of synchronous acquisition with the reception of the synchronous channel. In that way the transmission performance of the help signal is enhanced. CONSTITUTION: A BS(base station) reserves a help signal for a predetermined number of preamble for help signal of terminals of the coverage outside a reservation(401). The base station implements a signal reception with the other nodes with the rest preamble except a preamble(403). It looks at within the coverage of the base station from the specific terminal the presence of the help signal generation terminal and the base station receives a message(405). The base station assigns the amble for the urgency call service relay to the specific terminal(407).
Abstract translation: 目的：一种用于在无线蜂窝通信系统中发送紧急呼叫的装置和方法，能够增加帮助信号的检测率，提供能够通过接收同步信道同步采集的终端的高效紧急呼叫传输策略。 以这种方式，帮助信号的传输性能得到提高。 构成：BS（基站）为预留的覆盖的终端的帮助信号保留用于预定数量的前导码的帮助信号（401）。 基站除了前导码（403）之外，与其余节点实现与剩余前同步码的信号接收。 它在特定终端的基站的覆盖范围内查看帮助信号生成终端和基站的存在接收到消息（405）。 基站将用于紧急呼叫业务中继的业务分配给特定终端（407）。
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公开(公告)号：KR100855991B1
公开(公告)日：2008-09-02
申请号：KR1020070030048
申请日：2007-03-27
Applicant: 삼성전자주식회사 , 리전츠 오브 더 유니버시티 오브 캘리포니아
IPC: H01L27/115 , B82Y10/00
CPC classification number: H01L29/792 , H01L21/28273 , H01L21/28282 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L29/66825 , H01L29/66833 , H01L29/7926 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2924/01019 , H01L2924/15311 , H01L21/76897 , H01L2924/00014 , H01L2924/00012
Abstract: A non-volatile memory device and a manufacturing method thereof are provided to increase integration degree of a substrate by reducing a diameter or a width of a semiconductor pillar. A first doping layer(115) of a first conductive type is formed on a substrate(105). A semiconductor pillar(120) of a second conductive type is formed on the first doping layer. The second conductive type is opposite to the first conductive type. A control gate electrode(150a) is formed to surround a sidewall of the semiconductor pillar. An electric charge storage layer(140a) is inserted between the semiconductor pillar and the control gate electrode. A second doping layer(130) of the first conductive type is arranged on the second semiconductor pillar in order to be electrically connected to the semiconductor pillar.
Abstract translation: 提供了一种非易失性存储器件及其制造方法，以通过减小半导体柱的直径或宽度来增加衬底的集成度。 在衬底（105）上形成第一导电类型的第一掺杂层（115）。 在第一掺杂层上形成第二导电类型的半导体柱（120）。 第二导电类型与第一导电类型相反。 控制栅电极（150a）形成为围绕半导体柱的侧壁。 电荷存储层（140a）插入在半导体柱和控制栅电极之间。 第一导电类型的第二掺杂层（130）被布置在第二半导体柱上以与半导体柱电连接。
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