-
公开(公告)号：KR102235578B1
公开(公告)日：2021-04-02
申请号：KR1020140161943A
申请日：2014-11-19
Applicant: 삼성전자주식회사
IPC: H01L29/78
Abstract: 반도체 장치 및 그 제조 방법이 제공된다. 상기 반도체 장치는, 제1 방향으로 연장되어 형성되는 액티브 핀, 액티브 핀 상에 형성되고, 제1 방향과 교차하는 제2 방향으로 연장되는 게이트, 액티브 핀의 상부에 형성되고, 게이트의 일측에 배치되는 소오스 또는 드레인, 게이트와 소오스 또는 드레인을 덮는 층간 절연막, 층간 절연막을 관통하여 소오스 또는 드레인과 연결되고, 제1 콘택 영역과 제1 콘택 영역의 하부에 위치하는 제2 콘택 영역을 포함하는 소오스 또는 드레인 콘택 및 제1 콘택 영역과 층간 절연막 사이에 형성되는 스페이서막을 포함하되, 제1 콘택 영역의 제1 방향 폭과 제2 콘택 영역의 제1 방향 폭은, 제1 콘택 영역과 제2 콘택 영역의 경계에서 서로 다르다.
-
公开(公告)号：KR100889361B1
公开(公告)日：2009-03-18
申请号：KR1020060100947
申请日：2006-10-17
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/792 , H01L29/66833 , H01L29/7926
Abstract: 전자 주입 효율이 증가하고, 고집적도에 유리한 메모리 소자 및 이의 제조 방법이 제공된다. 메모리 소자는 바닥부, 및 바닥부로부터 수직하게 돌출되어 있는 수직부를 포함하되, 수직부는 경계단을 중심으로 상부에 위치하는 제1 수직부, 및 하부에 위치하며, 제1 수직부보다 폭이 크고, 제1 수직부의 외측으로 돌출되어 있는 제2 수직부를 포함하는 반도체 기판, 제1 수직부의 외측 및 경계단의 상부에 위치하는 전하 트랩층, 및 바닥부의 상부 및 제2 수직부와 전하 트랩층의 외측에 위치하는 컨트롤 게이트 전극을 포함한다.
플래쉬 메모리 소자, 수직부, 전자 주입 효율, 자기 정렬-
3.发明授权경사진 측벽을 갖는 활성 필라를 구비하는 비휘발성 메모리트랜지스터, 이를 구비하는 비휘발성 메모리 어레이 및상기 비휘발성 메모리 트랜지스터의 제조방법 有权非易失性存储器晶体管，包括具有斜面的活动支柱，具有晶体管的非易失性存储器阵列，以及制造晶体管的方法
公开(公告)号：KR100855992B1
公开(公告)日：2008-09-02
申请号：KR1020070032517
申请日：2007-04-02
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
IPC: H01L27/115
CPC classification number: H01L21/28282 , H01L21/28132 , H01L27/115 , H01L27/11568 , H01L29/1037 , H01L29/42332 , H01L29/42348 , H01L29/66787 , H01L29/7887 , H01L29/7923 , H01L29/7926 , H01L27/2463
Abstract: A non-volatile memory transistor including an active pillar having a sloped sidewall, a non-volatile memory array having the same, and a method for fabricating the same are provided to reduce power consumption by improving program efficiency. An active pillar(P) is protruded from a semiconductor substrate(10). The active pillar includes a sloped sidewall formed continuously from a surface of the semiconductor substrate. A gate electrode is formed to surround the sloped sidewall of the active pillar. An electric charge storage layer(23) is inserted between the active pillar and the gate electrode. A drain region(10d) is formed in an inside of an upper region of the active pillar. A source region(10s) is formed in the inside of the semiconductor substrate adjacent to a lower region of the active pillar.
Abstract translation: 提供了包括具有倾斜侧壁的有源支柱，具有其的非易失性存储器阵列及其制造方法的非易失性存储器晶体管，以通过提高程序效率来降低功耗。 活性柱（P）从半导体衬底（10）突出。 活性柱包括从半导体衬底的表面连续形成的倾斜侧壁。 栅电极形成为围绕有源支柱的倾斜侧壁。 电荷存储层（23）插入有源柱和栅电极之间。 漏极区域（10d）形成在有源支柱的上部区域的内部。 源极区域（10s）形成在与活性柱的下部区域相邻的半导体衬底的内部。
-
公开(公告)号：KR1020080034685A
公开(公告)日：2008-04-22
申请号：KR1020060100947
申请日：2006-10-17
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/792 , H01L29/66833 , H01L29/7926 , H01L21/28282 , H01L21/31144
Abstract: An NVM(non-volatile memory) device is provided to improve electron injection efficiency by making the injection direction of electrons passing through the bottom surface of a charge trap layer have the transfer direction of electrons. A semiconductor substrate(104) includes a bottom part(104c) and a vertical part vertically protruding from the bottom part. The vertical part includes first and second vertical parts(104a,104b). A first vertical part is positioned in the upper part of the semiconductor substrate with respect to a boundary step. The second vertical part is positioned under the first vertical part, greater in width than the first vertical part and protruding to the outside of the first vertical part. A charge trap layer(134) is positioned outside the first vertical part and on the boundary step. A control gate electrode(150) is positioned on the bottom part and outside the second vertical part and the charge trap layer. A first insulation layer(124) can be interposed between the semiconductor substrate and the charge trap layer. A second insulation layer(144) can be interposed between the semiconductor substrate and the control gate electrode.
Abstract translation: 提供NVM（非易失性存储器）器件以通过使通过电荷陷阱层的底表面的电子的注入方向具有电子的传输方向来提高电子注入效率。 半导体衬底（104）包括底部（104c）和从底部垂直突出的垂直部分。 垂直部分包括第一和第二垂直部分（104a，104b）。 相对于边界步骤，第一垂直部分位于半导体衬底的上部。 第二垂直部分位于第一垂直部分下方，宽度大于第一垂直部分并且突出到第一垂直部分的外侧。 电荷捕获层（134）位于第一垂直部分的外侧和边界台阶上。 控制栅电极（150）位于第二垂直部分和电荷陷阱层的底部和外部。 第一绝缘层（124）可以插入在半导体衬底和电荷陷阱层之间。 可以在半导体衬底和控制栅电极之间插入第二绝缘层（144）。
-
公开(公告)号：KR101800438B1
公开(公告)日：2017-11-23
申请号：KR1020100110033
申请日：2010-11-05
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11582 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/0649 , H01L29/7926
Abstract: 3차원반도체장치및 그제조방법이제공된다. 이장치는차례로적층된도전패턴들을포함하면서하부구조체상에배치되는상부구조체, 상부구조체를관통하여하부구조체에연결되는반도체패턴, 그리고반도체패턴과상부구조체사이에개재된절연스페이서를포함하며, 절연스페이서의바닥면은수직적위치에있어서하부구조체의가장높은상부면위에위치한다.
Abstract translation: 提供了一种三维半导体器件及其制造方法。 该装置包括介于之间的绝缘间隔件和包括顺序地堆叠的导电图案下部结构的上部结构设置在贯通连接到下部结构图案上部结构的半导体，以及半导体图案和上部结构，孤立 间隔件的底面以垂直位置定位在底座的最高的上表面上。
-
Patent Agency Ranking
公开(公告)号：KR101719217B1
公开(公告)日：2017-03-24
申请号：KR1020100064415
申请日：2010-07-05
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247 , H01L27/108 , H01L21/8242
CPC classification number: H01L27/11582 , H01L27/1157
Abstract: 3차원반도체장치및 그제조방법이제공된다. 이장치는차례로적층된도전패턴들을포함하면서기판상에배치되는도전구조체, 도전구조체를관통하여기판의상부면에삽입되는반도체패턴, 및반도체패턴과도전구조체사이에개재되는절연막구조체를포함한다. 반도체패턴은수평적으로연장되어절연막구조체의아래에서기판의측벽과직접접촉한다.
-
公开(公告)号：KR1020130019644A
公开(公告)日：2013-02-27
申请号：KR1020110081736
申请日：2011-08-17
Applicant: 삼성전자주식회사
CPC classification number: G11C5/025 , G11C5/063 , G11C7/18 , G11C8/14 , H01L27/228 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/146 , H01L45/147
Abstract: PURPOSE: A semiconductor memory device is provided to improve reliability by reducing a leakage current through unselected memory cells among three-dimensionally arranged memory cells. CONSTITUTION: A plurality of first word line structures are laminated in a first laminate structure. First word line structures include first word lines and a first connection pad. A first connection(INC1) is arranged on a first connection region(CNR1) with the same height from a substrate and is connected to the fist connection pad of each first word line structure. The length of the first connection pad in a second direction is equal to the product of the minimum pitch of first connection lines and the number of the laminated first word line structures.
Abstract translation: 目的：提供一种半导体存储器件，通过减少在三维布置的存储单元中的未选择存储单元的泄漏电流来提高可靠性。 构成：多个第一字线结构被层叠在第一层叠结构中。 第一字线结构包括第一字线和第一连接垫。 第一连接（INC1）被布置在与基板相同的高度的第一连接区域（CNR1）上，并且连接到每个第一字线结构的第一连接焊盘。 第一连接焊盘在第二方向上的长度等于第一连接线的最小间距和层叠的第一字线结构的数量的乘积。
-
公开(公告)号：KR1020120058222A
公开(公告)日：2012-06-07
申请号：KR1020100119904
申请日：2010-11-29
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/762 , H01L21/76224 , H01L27/1157 , H01L27/11582 , H01L21/02362 , H01L27/0688
Abstract: PURPOSE: A method for manufacturing a 3D semiconductor memory device is provided to minimize stress added a vertical type activity pattern by forming pads of a terraced structure at a sub-flat board laminate structure. CONSTITUTION: A flat board laminate structure including flat board insulating patterns(105s) and flat board sacrificed patterns(107s) is formed at the upper side of a substrate(100). The flat board insulating pattern and the flat board sacrificed pattern are repetitively laminated. A pad of a terraced structure is formed at the edge of the flat board sacrificed patterns. A first trench(120) divides the flat board laminate structure into a plurality of sub-flat board laminate structures(110s). A plurality of vertical type activity patterns(140) passes through each sub-flat board laminate structure. A second trench divides each sub-flat board laminate structure into a plurality of mold-laminate structures.
Abstract translation: 目的：提供一种用于制造3D半导体存储器件的方法，通过在亚平板层压结构上形成梯形结构的焊盘来最小化施加垂直型活动模式的应力。 构成：在基板（100）的上侧形成包括平板绝缘图案（105s）和平板处理图案（107s）的平板层叠结构。 平板绝缘图案和平板处理图案被重复层压。 在平板的牺牲图案的边缘处形成梯形结构的垫。 第一沟槽（120）将平板层叠结构分成多个亚平板层压结构（110s）。 多个垂直型活动图案（140）穿过每个亚平板层压结构。 第二沟槽将每个亚平板层压结构分成多个模层叠结构。
-
公开(公告)号：KR1020110080183A
公开(公告)日：2011-07-13
申请号：KR1020100000287
申请日：2010-01-05
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/7682 , H01L21/02164 , H01L21/02266 , H01L23/5222 , H01L2924/0002 , H01L21/28273 , H01L29/45 , H01L2924/00
Abstract: PURPOSE: A semiconductor device, a semiconductor device fabricating method and a wiring structure forming method are provided to make it possible adjusting a size of an air gap to a thickness of an oxide pattern. CONSTITUTION: The first oxide thin film(157c) is formed by depositing an oxygen component, separated from the first oxide film patterns, on sidewalls of gate structures namely a tunnel insulating film(110) or a substrate(100) when a sputtering process is performed. In case that the sputtering process is performed by using oxygen gas, the first oxide thin film can be deposited on the sidewalls of the gate structures by plasma oxide. The total oxide films is the second oxide film structure(157) which includes an upper part(157a), a side part(157b) and the first oxide thin film. The side part of the second oxide thin film structure, the sidewalls of the gate structure, the tunnel insulating film or the substrate can define the second air gap(164).
Abstract translation: 目的：提供半导体器件，半导体器件制造方法和布线结构形成方法，以便可以将气隙的尺寸调整为氧化物图案的厚度。 构成：当溅射过程是在溅射过程是在第二氧化物薄膜图案上分离的氧化物组分时，在栅极结构的侧壁（即隧道绝缘膜）或基底（100）上形成第一氧化物薄膜（157c） 执行。 在通过使用氧气进行溅射处理的情况下，可以通过等离子体氧化物将第一氧化物薄膜沉积在栅极结构的侧壁上。 总氧化膜是包括上部（157a），侧面部（157b）和第一氧化物薄膜的第二氧化膜结构（157）。 第二氧化物薄膜结构的侧面部分，栅极结构的侧壁，隧道绝缘膜或基底可以限定第二气隙（164）。
-
公开(公告)号：KR1020090009638A
公开(公告)日：2009-01-23
申请号：KR1020070073092
申请日：2007-07-20
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L21/28282 , H01L27/11565 , H01L27/11568
Abstract: A nonvolatile memory element is provided to reduce an electric field by using a second blocking insulation film and reduce trap charge density by using a first blocking insulation film, thereby lengthening a retention time of a device and reducing back tunneling currents during an erase operation. A nonvolatile memory element comprises a tunnel insulating layer formed on a semiconductor substrate, a charge trapping layer formed on the tunnel insulating layer, a blocking insulation film formed on the charge trapping layer, and a control gate electrode formed on the blocking insulation film. The blocking insulation film more includes a first blocking insulation film and a second blocking insulation film. At this time, the bulk trap density of the first blocking insulation film is smaller than the bulk trap density of the second blocking insulation film. The first blocking insulation film is arranged between the charge trapping layer and the second blocking insulation film. The second blocking insulation film uses a high dielectric insulating layer in which a dielectric rate is larger than the tunnel insulating layer. The thickness of the first blocking insulation film is 1 nm to 100 nm. The thickness of the second blocking insulation film is 1 to 100 nm.
Abstract translation: 提供了一种非易失性存储元件，通过使用第二阻挡绝缘膜来减少电场，并通过使用第一阻挡绝缘膜来减小陷阱电荷密度，从而延长器件的保持时间并减少擦除操作期间的隧穿电流。 非易失性存储元件包括形成在半导体衬底上的隧道绝缘层，形成在隧道绝缘层上的电荷俘获层，形成在电荷俘获层上的阻挡绝缘膜，以及形成在阻挡绝缘膜上的控制栅电极。 阻挡绝缘膜更包括第一阻挡绝缘膜和第二阻挡绝缘膜。 此时，第一阻挡绝缘膜的体积陷阱密度小于第二阻挡绝缘膜的体积陷阱密度。 第一阻挡绝缘膜布置在电荷俘获层和第二阻挡绝缘膜之间。 第二阻挡绝缘膜使用电介质率大于隧道绝缘层的高介电绝缘层。 第一阻挡绝缘膜的厚度为1nm〜100nm。 第二阻挡绝缘膜的厚度为1〜100nm。
-
-
-
-
-
-
-
-
-
Search Results
50
records
(took 0.033 seconds)
