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    Programmable logic with hierarchical interconnects
    1.
    发明专利
    Programmable logic with hierarchical interconnects 未知

    公开(公告)号：GB2346725A

    公开(公告)日：2000-08-16

    申请号：GB0011200

    申请日：1997-09-26

    Applicant: ALTERA CORP

    Inventor： REDDY SRINIVAS T ,  CLIFF RICHARD G ,  LANE CHRISTOPHER F ,  ZAVERI KETAN H ,  MEJIA MANUAL M ,  PEDERSON BRUCE B ,  JEFFERSON DAVID E ,  LEE ANY L

    IPC: H03K19/177

    Abstract: A programmable logic device has a two-dimensional array of intersecting rows and columns of super-regions of programmable logic. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

    Programmable logic device with hierarchical interconnection resources
    2.
    发明专利
    Programmable logic device with hierarchical interconnection resources 未知

    公开(公告)号：GB2318199B

    公开(公告)日：2000-12-13

    申请号：GB9720543

    申请日：1997-09-26

    Applicant: ALTERA CORP

    Inventor： REDDY SRINIVAS T ,  CLIFF RICHARD G ,  LANE CHRISTOPHER F ,  ZAVERI KETAN H ,  MEJIA MANUAL M ,  PEDERSEN BRUCE ,  JEFFERSON DAVID E ,  LEE ANY L

    IPC: H01L21/82 ,  H03K19/177

    Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stiching together axial segments to make longer connectors.

    PROGRAMMABLE LOGIC DEVICE STRUCTURE
    4.
    发明专利
    PROGRAMMABLE LOGIC DEVICE STRUCTURE 失效

    公开(公告)号：JP2000201066A

    公开(公告)日：2000-07-18

    申请号：JP32754999

    申请日：1999-11-17

    Applicant: ALTERA CORP

    Inventor： JEFFERSON DAVID E ,  CAMERON MCCLINTOCK ,  SCHLEICHER JAMES ,  ANDY L LEE ,  MEJIA MANUEL ,  PEDERSEN BRUCE B ,  LANE CHRISTOPHER F ,  CLIFF RICHARD G ,  SURINIBASU T REDI

    IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

    Abstract: PROBLEM TO BE SOLVED: To provide a large capacity programmable logic device structure capable of eliminating the need for any excessive amount of interconnection conductor resources on a device. SOLUTION: In a programmable logic device 10, plural large areas 20 arranged in a second-dimensional array constituted of crossing lines and columns are provided on this device. Each large area 20 is provided with plural programmable logic areas 30 and a programmable memory area 40. Each logic area 30 is provided with plural small areas 50 constituted of programmable logics. Each large area 20 is provided with connected interconnection resources so that communication between the logics in the large area and the memory area 40 can be attained without using any huge inter-large area interconnection resources arranged on this device in the same way for relative local interconnection.

    5.
    发明专利
    未知

    公开(公告)号：DE69933525T2

    公开(公告)日：2007-04-05

    申请号：DE69933525

    申请日：1999-11-15

    Applicant: ALTERA CORP

    Inventor： JEFFERSON DAVID E ,  LEE ANDY L ,  LANE CHRISTOPHER F ,  MCCLINTOCK CAMERON ,  MEJIA MANUEL ,  CLIFF RICHARD G ,  SCHLEICHER JAMES ,  PEDERSON BRUCE B ,  REDDY SRINIVAS T

    IPC: H01L21/82 ,  H03K19/177 ,  H03K19/173

    Abstract: A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

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