公开(公告)号：GB2333873A

公开(公告)日：1999-08-04

申请号：GB9909313

申请日：1996-05-14

Applicant: ALTERA CORP

Inventor： CLIFF RICHARD G ,  REDDY SRINIVAS T ,  JEFFERSON DAVID E ,  RAMAN RINA ,  COPE L TODD ,  LANE CHRISTOPHER F ,  HUANG JOSEPH ,  HEILE FRANCIS B ,  PEDERSON BRUCE B ,  MENDEL DAVID WOLK ,  LYTLE CRAIG SCHILLING ,  BIELBY ROBERT RICHARD NOEL ,  VEENSTRA KERRY

IPC: H03K19/173 ,  H03K19/177

Abstract: A programmable logic array integrated circuit device includes a plurality of programmable logic modules 30 each programmable to perform any of a plurality of logic functions and having a register (flip-flop) 34. When a global clear mode is programmed 574, a signal applied to a (global) clear input terminal 570 can clear all the registers 34 via a global clear conductor 576.

公开(公告)号：GB2346725A

公开(公告)日：2000-08-16

申请号：GB0011200

申请日：1997-09-26

Applicant: ALTERA CORP

Inventor： REDDY SRINIVAS T ,  CLIFF RICHARD G ,  LANE CHRISTOPHER F ,  ZAVERI KETAN H ,  MEJIA MANUAL M ,  PEDERSON BRUCE B ,  JEFFERSON DAVID E ,  LEE ANY L

IPC: H03K19/177

Abstract: A programmable logic device has a two-dimensional array of intersecting rows and columns of super-regions of programmable logic. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

公开(公告)号：GB2306727B

公开(公告)日：2000-02-16

申请号：GB9621052

申请日：1996-10-09

Applicant: ALTERA CORP

Inventor： KAZARIAN PETER J ,  PEDERSON BRUCE B ,  HEILE FRANCIS BERNARD ,  MENDEL DAVID WOLK

IPC: H03K19/177

Abstract: Logic signal routability in programmable logic array integrated circuit devices is improved by selecting the possible interconnections between various resources on the device so that various constraints or goals are satisfied. Improving routability in this way tends to reduce instances in which desired interconnections are blocked by other connections that have already been made.

公开(公告)号：DE69933525T2

公开(公告)日：2007-04-05

申请号：DE69933525

申请日：1999-11-15

Applicant: ALTERA CORP

Inventor： JEFFERSON DAVID E ,  LEE ANDY L ,  LANE CHRISTOPHER F ,  MCCLINTOCK CAMERON ,  MEJIA MANUEL ,  CLIFF RICHARD G ,  SCHLEICHER JAMES ,  PEDERSON BRUCE B ,  REDDY SRINIVAS T

IPC: H01L21/82 ,  H03K19/177 ,  H03K19/173

Abstract: A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

公开(公告)号：DE69223010D1

公开(公告)日：1997-12-11

申请号：DE69223010

申请日：1992-08-06

Applicant: ALTERA CORP

Inventor： PEDERSON BRUCE B ,  CLIFF RICHARD G ,  AHANIN BAHRAM ,  LYTLE CRAIG SCHILLING ,  HEILE FRANCIS B ,  VEENSTRA KERRY SCOTT

IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

Abstract: A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

公开(公告)号：GB2346725B

公开(公告)日：2000-12-13

申请号：GB0011200

申请日：1997-09-26

Applicant: ALTERA CORP

Inventor： REDDY SRINIVAS T ,  CLIFF RICHARD G ,  LANE CHRISTOPHER F ,  ZAVERI KETAN H ,  MEJIA MANUAL M ,  PEDERSON BRUCE B ,  JEFFERSON DAVID E ,  LEE ANY L

IPC: H03K19/177

公开(公告)号：GB2346724B

公开(公告)日：2000-12-06

申请号：GB0011195

申请日：1997-09-26

Applicant: ALTERA CORP

Inventor： REDDY SRINIVAS T ,  CLIFF RICHARD G ,  LANE CHRISTOPHER F ,  ZAVERI KETAN H ,  MEJIA MANUAL M ,  PEDERSON BRUCE B ,  JEFFERSON DAVID E ,  LEE ANY L

IPC: H03K19/177

公开(公告)号：GB2333874B

公开(公告)日：1999-09-22

申请号：GB9909316

申请日：1996-05-14

Applicant: ALTERA CORP

Inventor： CLIFF RICHARD G ,  REDDY SRINIVAS T ,  JEFFERSON DAVID E ,  RAMAN RINA ,  COPE L TODD ,  LANE CHRISTOPHER F ,  HUANG JOSEPH ,  HEILE FRANCIS B ,  PEDERSON BRUCE B ,  MENDEL DAVID WOLK ,  LYTLE CRAIG SCHILLING ,  BIELBY ROBERT RICHARD NOEL ,  VEENSTRA KERRY

IPC: H03K19/173 ,  H03K19/177

公开(公告)号：GB2333874A

公开(公告)日：1999-08-04

申请号：GB9909316

申请日：1996-05-14

Applicant: ALTERA CORP

Inventor： CLIFF RICHARD G ,  REDDY SRINIVAS T ,  JEFFERSON DAVID E ,  RAMAN RINA ,  COPE L TODD ,  LANE CHRISTOPHER F ,  HUANG JOSEPH ,  HEILE FRANCIS B ,  PEDERSON BRUCE B ,  MENDEL DAVID WOLK ,  LYTLE CRAIG SCHILLING ,  BIELBY ROBERT RICHARD NOEL ,  VEENSTRA KERRY

IPC: H03K19/173 ,  H03K19/177

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic with a universal signal conductor extending adjacent each region. A first programmable switch is associated with each region for selectively applying a signal on the universal signal conductor to the region as an input signal. A second programmable switch is provided for selectively applying to the universal signal conductor either a signal received by an input pin or an output signal from one of the regions.

公开(公告)号：GB2333872A

公开(公告)日：1999-08-04

申请号：GB9909312

申请日：1996-05-14

Applicant: ALTERA CORP

Inventor： CLIFF RICHARD G ,  REDDY SRINIVAS T ,  JEFFERSON DAVID E ,  RAMAN RINA ,  COPE L TODD ,  LANE CHRISTOPHER F ,  HUANG JOSEPH ,  HEILE FRANCIS B ,  PEDERSON BRUCE B ,  MENDEL DAVID WOLK ,  LYTLE CRAIG SCHILLING ,  BIELBY ROBERT RICHARD NOEL ,  VEENSTRA KERRY

IPC: H03K19/173 ,  H03K19/177

Abstract: A programmable logic array integrated circuit device includes a plurality of programmable logic modules (Fig. 8 shows one), each programmable to produce an intermediate signal 52 which is any of a plurality of logic functions of input signals A-D, a programmable switch 530 selectively applying the intermediate signal or input signal D to a register 34 to register it, a programmable switch 540a selectively applying the intermediate signal or the registered signal to a first output 100, and a programmable switch 540b selectively applying the intermediate signal or the registered signal to a second output 38.