公开(公告)号：JP2004279403A

公开(公告)日：2004-10-07

申请号：JP2003359976

申请日：2003-09-11

Applicant: Asml Netherlands Bv ,  エイエスエムエル ネザランドズ ベスローテン フエンノートシャップ

Inventor： BEST KEITH FRANK ,  CONSOLINI JOSEPH ,  FRIZ ALEXANDER ,  VAN BUEL HENRICUS WILHELMUS MA

IPC: G01B11/00 ,  G01B11/26 ,  G03F9/00 ,  H01L21/027

CPC classification number: G03F9/7015

Abstract: PROBLEM TO BE SOLVED: To provide a method for which substrate (wafer) alignment to a reference mark is improved.
SOLUTION: While the alignment beam is focused on the mark on the substrate table, the substrate table is moved substantially perpendicular to the alignment beam. If the image of the mark moves relative to the reference mark, the substrate and the alignment beam will not be perpendicular. The positions of the marks on the substrate table are adjusted so as to coincide with those of a plurality of reference marks. Although at least two substrate marks are aligned with a single reference mark, errors due to inclination of the alignment beam are excluded from the expansion and rotation values calculated with respect to the substrate.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2006186369A

公开(公告)日：2006-07-13

申请号：JP2005372013

申请日：2005-12-26

Applicant: ASML NETHERLANDS BV

Inventor： BEST KEITH FRANK ,  CONSOLINI JOSEPH J ,  FRIZ ALEXANDER ,  CHISHOLM RODNEY

IPC: H01L21/027 ,  G03F7/20 ,  H01L21/02 ,  H01L21/68

Abstract: PROBLEM TO BE SOLVED: To provide a wafer which is a semiconductor wafer of which surfaces on both sides can be polished to any degree. SOLUTION: One side of a semiconductor wafer is polished to comparatively higher degree that is suitable for making a fine pattern by a lithography process, and the other side thereof is polished to comparatively low degree, that is appropriate to provide alignment marks WM3 and WM4 effective for arranging wafers in the lithography process. COPYRIGHT: (C)2006,JPO&NCIPI

公开(公告)号：JP2004165670A

公开(公告)日：2004-06-10

申请号：JP2003382650

申请日：2003-11-12

Applicant: Asml Netherlands Bv ,  エイエスエムエル ネザランドズ ベスローテン フエンノートシャップ

Inventor： BEST KEITH FRANK ,  CONSOLINI JOSEPH J ,  FRIZ ALEXANDER

IPC: G03F9/00 ,  G03C5/00 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F9/7003

Abstract: PROBLEM TO BE SOLVED: To provide a device manufacturing method which can print on one side of a substrate with improved precision after aligning the substrate by referring to the markers provided on the other side of the substrate without using additional hardware.
SOLUTION: This device manufacturing method comprises a process of preparing a first substrate W having a first surface 10a and a second surface 10b, a process of forming a pattern composed of at least one inversion alignment marking (1-8) on the first surface of the first substrate, a process of providing a protective layer 11 on the alignment marking, a process of joining the first surface of the first substrate to a second substrate CW, a process of locally etching the first substrate to the protective layer to form a trench 17 around the inversion alignment marking, and a process of using a lithographic projection apparatus having a front/rear alignment unit to align the substrates by referring to the alignment marking which is enclosed by the trench and to form at least one patterned layer 15 on the second surface.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2006186367A

公开(公告)日：2006-07-13

申请号：JP2005371940

申请日：2005-12-26

Applicant: ASML NETHERLANDS BV

Inventor： BEST KEITH FRANK ,  CONSOLINI JOSEPH J

IPC: H01L21/027 ,  G03F7/20

Abstract: PROBLEM TO BE SOLVED: To provide a technique capable of positioning a 2nd substrate joined to the top surface of a 1st substrate which has a thickness of >100 μm and is preferably pattern-formed and implementing the positioning at reduced cost within a limited time. SOLUTION: A forming method is provided for a junction substrate including a stage of providing the 1st substrate which has a 1st substrate shape and also has at least alignment mark disposed on a 1st surface side. A 2nd substrate is provided having the 2nd substrate shape. The 2nd substrate is directed in a designated direction to the 1st substrate. The 2nd substrate is joined to the 1st surface side of the 1st substrate, so that the 2nd substrate which is joined does not cover at least one 1st alignment mark, thus providing the junction substrate. COPYRIGHT: (C)2006,JPO&NCIPI

公开(公告)号：JP2005191570A

公开(公告)日：2005-07-14

申请号：JP2004371085

申请日：2004-12-22

Applicant: Asml Netherlands Bv ,  エイエスエムエル ネザランドズ ベスローテン フエンノートシャップ

Inventor： CONSOLINI JOSEPH J ,  BEST KEITH FRANK ,  FRIZ ALEXANDER

IPC: G01B11/00 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027

CPC classification number: G03F9/7003 ,  G03F9/7076 ,  G03F9/7084

Abstract: PROBLEM TO BE SOLVED: To provide a measuring method, a method of providing an alignment mark and to provide a device manufacturing method.
SOLUTION: According to the measuring method by one embodiment, the relative mark between the provisional alignment mark of one surface in a substrate and the alignment mark of the other surface thereof is determined, and the provisional alignment mark is removed. Prior to the removal of the provisional alignment mark, the relative position between the provisional alignment mark and the other mark on the same surface of the substrate can be determined. The provisional alignment mark, for example, can be formed on an oxide layer on the substrate.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供测量方法，提供对准标记的方法并提供器件制造方法。 解决方案：根据一个实施例的测量方法，确定衬底中一个表面的临时对准标记与其另一个表面的对准标记之间的相对标记，并且去除临时对准标记。 在移除临时对准标记之前，可以确定临时对准标记与衬底的相同表面上的另一个标记之间的相对位置。 临时对准标记例如可以形成在基板上的氧化物层上。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2008160083A

公开(公告)日：2008-07-10

申请号：JP2007300100

申请日：2007-11-20

Applicant: Asml Netherlands Bv ,  エーエスエムエル ネザーランズ ビー.ブイ.

Inventor： BEST KEITH FRANK ,  GUI CHENG-QUN ,  DAVID CHRISTOPHER OCKWELL ,  TEN BERGE PETER

IPC: H01L21/60

CPC classification number: H01L21/6835 ,  H01L21/67115 ,  H01L24/80 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a device which forms a ring-shaped resist pattern for forming bumps in a substrate by electrodepositing.
SOLUTION: The apparatus includes a substrate holder arranged to hold a substrate W coated at least in part with resist R, and a heating device configured to heat an area of the resist. The relative movement between the substrate holder and the heating device HD is possible. The movement is arranged such that, in use of the ring seal forming apparatus, the area of resist heated by the heating device HD is ring-shaped, so that the ring-shaped resist pattern can be formed.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过电沉积形成用于在基板中形成凸块的环形抗蚀剂图案的装置。 解决方案：该装置包括衬底保持器，其被布置成保持至少部分地涂覆有抗蚀剂R的衬底W;以及加热装置，其构造成加热抗蚀剂的区域。 衬底保持器和加热装置HD之间的相对运动是可能的。 该移动被配置为使用环形密封形成装置，由加热装置HD加热的抗蚀剂的面积是环状的，从而可以形成环状的抗蚀剂图案。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006186377A

公开(公告)日：2006-07-13

申请号：JP2005375546

申请日：2005-12-27

Applicant: ASML NETHERLANDS BV

Inventor： BEST KEITH FRANK ,  PHILLIPPS GEOFFREY NORMAN ,  BIJNEN FRANCISCUS GODEFRIDUS C ,  VAN DEN BRINK ENNO ,  VAN BUEL HENRICUS WILHELMUS MA ,  CONSOLINI JOSEPH J ,  TEN BERGE PETER

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for three-dimensional alignment for wafer scale integration. SOLUTION: A board bonding system is provided with first and second board tables to hold first and second boards, and a controller. The first board is equipped with a first device having a first contact pad, and the second board is equipped with a second device having a second contact pad. The wafer bonding system is designed to conduct bonding of the first and second devices so that a circuit can be formed by the first and second devices. First and second board tables ST and STb are respectively provided with a position sensor to measure optical signals generating on alignment markers WM1, WM1', WM2, and WM2', and WM1b, WM1b', WM2b and WM2b' of the first and second boards. Furthermore, they are provided with first and second actuators ACT and ACTb to change the position and the orientation of the respective board tables. COPYRIGHT: (C)2006,JPO&NCIPI

公开(公告)号：JP2004207732A

公开(公告)日：2004-07-22

申请号：JP2003423526

申请日：2003-12-19

Applicant: Asml Netherlands Bv ,  エイエスエムエル ネザランドズ ベスローテン フエンノートシャップ

Inventor： BEST KEITH FRANK ,  CONSOLINI JOSEPH J ,  SHINDE SHYAM

IPC: G03F7/20 ,  G03F9/00 ,  H01L21/027 ,  H01L21/301 ,  H01L23/544

CPC classification number: G03F7/70425 ,  G03F7/70633 ,  G03F9/7003 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a device, where a circuit structure is exposed with improved precision on one side of a substrate positioned for a marker of the other side, when the substrate(e.g., resist-covered wafer) is bonded on a carrier wafer.
SOLUTION: In manufacturing the device on the substrate having first and second surfaces, a reverse alignment marker is etched up to a depth of 10 μm on the first surface of the substrate, and the substrate is reversed and is bonded on the carrier wafer, then the reverse alignment marker is lapped or polished up to a thickness of 10 μm, thereby the reverse alignment marker becomes visible as a normal alignment marker. The reverse alignment marker can include the normal and reverse overlaid markers.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2007043173A

公开(公告)日：2007-02-15

申请号：JP2006210417

申请日：2006-08-02

Applicant: Asml Netherlands Bv ,  エーエスエムエル ネザーランズ ビー.ブイ.

Inventor： BEST KEITH FRANK ,  JOHANNES WILHELMUS MARIA KRKHA ,  RUDY JAN MARIA PELLENS

IPC: H01L21/68 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F9/7011 ,  G03F7/70691 ,  G03F9/7003 ,  G03F9/7034 ,  G03F9/7084 ,  Y10S438/943 ,  Y10S438/946

Abstract: PROBLEM TO BE SOLVED: To provide a substrate holder for appropriately leveling a substrate separated from standard and a device manufacturing method. SOLUTION: A first substrate W1 is attached to a substrate table WT. Then, a second substrate W2 such as III/V compound semiconductor is positioned on the front surface 3 of the first substrate W1 such as wafer and a glass substrate. The first substrate W1 is aligned relative to a projection system so that a projection beam may be projected on the target portion C of the second substrate W2. The second substrate W2 is exposed to a radioactive ray which is pattern formed. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于使与标准分离的基板适当调平的基板保持器和装置制造方法。 解决方案：第一衬底W1附接到衬底台WT。 然后，将诸如III / V化合物半导体的第二衬底W2定位在诸如晶片和玻璃衬底的第一衬底W1的前表面3上。 第一基板W1相对于投影系统对准，使得投影光束可以投影在第二基板W2的目标部分C上。 第二基板W2暴露于形成图案的放射线。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007013192A

公开(公告)日：2007-01-18

申请号：JP2006203910

申请日：2006-06-28

Applicant: Asml Netherlands Bv ,  エーエスエムエル ネザーランズ ビー.ブイ.

Inventor： BEST KEITH FRANK ,  CONSOLINI JOSEPH J ,  FRIZ ALEXANDER ,  CASPER BIJNEN FRANCISCUS GODEF ,  TOLSMA HOITE PIETER THEODOOR ,  BERGE PETER T

IPC: H01L21/027 ,  G03F7/40 ,  G03F9/00

CPC classification number: G03F9/7019 ,  A41D2400/00 ,  G03F7/70633 ,  G03F9/7003 ,  G03F9/7011 ,  G03F9/7084 ,  G03F9/7088

Abstract: PROBLEM TO BE SOLVED: To provide a method for analyzing the behavior of front side marks on a substrate, during a process of manufacturing a device, without the need for etching global alignment marks.
SOLUTION: A plurality of front-side marks are manufactured on the front side of a substrate by a method for manufacturing a device, and these marks are used to locally align the substrate during exposure. After a certain number of processing steps, the positions of the front side marks are measured and compared with respect to their original positions. Next, the change, that is, their behavior, can be analyzed in the measured positions of the front side marks. The original positions and actual positions thereof are defined, with respect to a nominal grid which is defined by using global alignment marks which are positioned at the back side of the substrate. Because the global alignment marks are positioned on the back side, they will not be affected by any processing step.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于分析基板上的正面标记的行为的方法，在制造装置的过程中，不需要蚀刻全局对准标记。 解决方案：通过制造装置的方法在基板的正面上制造多个前侧标记，并且这些标记用于在曝光期间局部对准基板。 在一定数量的处理步骤之后，测量前侧标记的位置并相对于其原始位置进行比较。 接下来，可以在前侧标记的测量位置分析变化，即它们的行为。 关于通过使用位于基板的背面的全局对准标记限定的标称网格来定义其原始位置和实际位置。 因为全局对齐标记位于背面，所以它们不受任何处理步骤的影响。 版权所有（C）2007，JPO＆INPIT