公开(公告)号：JPS6369238A

公开(公告)日：1988-03-29

申请号：JP19654787

申请日：1987-08-07

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  JOHNSON DAVID LOUIS ,  PAN PAI-HUNG ,  PAQUETTE CHARLES ARTHUR

IPC: H01L21/316 ,  H01L21/265 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/51

公开(公告)号：DE3686453D1

公开(公告)日：1992-09-24

申请号：DE3686453

申请日：1986-05-16

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN ,  SEDGWICK THOMAS OLIVER ,  STIFFLER SCOTT RICHARD

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/205 ,  H01L21/18 ,  H01L21/306

Abstract: A method of forming a thin silicon layer (12A) upon which semiconductor devices may be constructed. An epitaxial layer (12A, 12B) is grown on a silicon substrate (10), and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer (14) therein. An oxide layer (16A) is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer (100). The silicon substrate (10) is removed using grinding and/or HNA, the upper portions (12B) of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop (14) is removed using a non-selective etch. The remaining portion of the epitaxy (12A) forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

公开(公告)号：DE3670402D1

公开(公告)日：1990-05-17

申请号：DE3670402

申请日：1986-01-17

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  KOBURGER III CHARLES WILLIAM

IPC: H01L27/08 ,  H01L21/20 ,  H01L21/225 ,  H01L21/76 ,  H01L21/762 ,  H01L29/78

Abstract: A process for making complementary transistor devices - (11, 12) in an epitaxial layer (14) of a first conductivity type having a deep vertical isolation sidewall (21) between the N and P channel transistors by providing a backfilled cavity - (26) in the epitaxial layer, the sidewalls of the cavity being coated with layers of material, the first layer being a silicate doped with the same conductivity type as the epitaxial layer (14) and in contact with the epitaxial layer. The first layer is overcoated with an isolation and diffusion barrier layer (21). A second silicate layer is provided which is doped to a conductivity opposite to that of the first layer and isolated therefrom by said isolation and diffusion barrier material (21). The cavity (26) is backfilled with semiconductor material of a conductivity type opposite to that of the epitaxial layer (14) and during this backfilling operation the dopants in the first and second layer outdiffuse into the epitaxial layer and into the backfill material, respectively, to prevent the creation of oarasitic channels.

公开(公告)号：DE3871457D1

公开(公告)日：1992-07-02

申请号：DE3871457

申请日：1988-07-12

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  CRONIN JOHN EDWARD ,  LASKY JEROME BRETT

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L21/90

公开(公告)号：DE3576883D1

公开(公告)日：1990-05-03

申请号：DE3576883

申请日：1985-05-24

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  KINNEY WAYNE IRVING ,  LASKY JEROME BRETT ,  STIFFLER SCOTT RICHARD

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/00 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792 ,  H01L21/76

Abstract: A shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide (40). The bulk semiconductor (24) underlying the insulating layer (40) is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer (40) is defined into another FET with its drain region (60) above the gate oxide (40), whereby the drain region (60) also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.

公开(公告)号：DE3686453T2

公开(公告)日：1993-03-18

申请号：DE3686453

申请日：1986-05-16

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN ,  SEDGWICK THOMAS OLIVER ,  STIFFLER SCOTT RICHARD

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/205 ,  H01L21/18 ,  H01L21/306

Abstract: A method of forming a thin silicon layer (12A) upon which semiconductor devices may be constructed. An epitaxial layer (12A, 12B) is grown on a silicon substrate (10), and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer (14) therein. An oxide layer (16A) is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer (100). The silicon substrate (10) is removed using grinding and/or HNA, the upper portions (12B) of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop (14) is removed using a non-selective etch. The remaining portion of the epitaxy (12A) forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

公开(公告)号：DE3774052D1

公开(公告)日：1991-11-28

申请号：DE3774052

申请日：1987-08-21

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  JOHNSON DAVID LOUIS ,  PAN PAI-HUNG ,  PAQUETTE CHARLES ARTHUR

IPC: H01L21/316 ,  H01L21/265 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/51

Abstract: The inventive method relates to the formation of a thin film of silicon oxynitride exhibiting a high breakdown voltage on a silicon substrate of a first conductivity type and comprises the steps of: forming a thin film of silicon oxynitride on the silicon substrate; forming a region of a second conductivity type in at least part of the silicon substrate by ion implantation through said thin film of silicon oxynitride; and annealing said silicon oxynitride film in a wet O2 ambient at a temperature between 700 DEG C and 1000 DEG C. Preferably the deposited layer is annealed additionally after the deposition and prior to the ion implantation. The method is applied in the formation of capacitor structures, like high capacitance storage capacitors for dynamic random access memory cells.