公开(公告)号：DE3686453T2

公开(公告)日：1993-03-18

申请号：DE3686453

申请日：1986-05-16

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN ,  SEDGWICK THOMAS OLIVER ,  STIFFLER SCOTT RICHARD

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/205 ,  H01L21/18 ,  H01L21/306

Abstract: A method of forming a thin silicon layer (12A) upon which semiconductor devices may be constructed. An epitaxial layer (12A, 12B) is grown on a silicon substrate (10), and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer (14) therein. An oxide layer (16A) is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer (100). The silicon substrate (10) is removed using grinding and/or HNA, the upper portions (12B) of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop (14) is removed using a non-selective etch. The remaining portion of the epitaxy (12A) forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

公开(公告)号：DE69425527D1

公开(公告)日：2000-09-21

申请号：DE69425527

申请日：1994-03-23

Applicant: IBM

Inventor： GEISSLER STEPHEN FRANK ,  KOREJWA JOSEF WARREN ,  LASKY JEROME BRETT ,  PAI PAI-HUNG

IPC: H01L21/318 ,  H01L21/314 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/28

Abstract: A silicon nitride layer in a semiconductor device is oxidized by exposure to a mixture of an oxygen reactant and a dilute amount of a fluorine-containing compound at a temperature sufficiently high to substantially cause the oxidation of the silicon nitride. Generally, a temperature greater than about 600 DEG C is sufficient to cause such oxidation, although some oxidation may occur at lower temperatures. The concentration of the fluorine-containing compound is also not critical, but is generally between about 100 to 1500 ppm by volume relative to the total mixture volume. Preferably, NF3 is the fluorine-containing compound, and a temperature greater than about 700 DEG C at a concentration of between about 100 to 1000 ppm is used.

公开(公告)号：DE3885637T2

公开(公告)日：1994-05-11

申请号：DE3885637

申请日：1988-03-08

Applicant: IBM

Inventor： LASKY JEROME BRETT

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/764 ,  H01L27/12

Abstract: The method comprises the steps of providing a layer of material on portions of the surface of a support structure; providing a polishing stop layer of substantially uniform thickness on different portions of the surface of said support structure, such that a first surface of said layer of material and a first surface of said polishing stop layer are substantially coplanar, said polishing stop layer being thinner than said layer of material; polishing the second surface of said layer of material to a point where a second surface of said polishing stop layer is encountered, such that the substantially uniform thickness of said polishing stop layer is used to define said layer of material to a layer of uniform thickness. In particular the method is used for forming improved silicon-on-insulator structures.

公开(公告)号：DE69425527T2

公开(公告)日：2001-04-26

申请号：DE69425527

申请日：1994-03-23

Applicant: IBM

Inventor： GEISSLER STEPHEN FRANK ,  KOREJWA JOSEF WARREN ,  LASKY JEROME BRETT ,  PAI PAI-HUNG

IPC: H01L21/318 ,  H01L21/314 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/28

Abstract: A silicon nitride layer in a semiconductor device is oxidized by exposure to a mixture of an oxygen reactant and a dilute amount of a fluorine-containing compound at a temperature sufficiently high to substantially cause the oxidation of the silicon nitride. Generally, a temperature greater than about 600 DEG C is sufficient to cause such oxidation, although some oxidation may occur at lower temperatures. The concentration of the fluorine-containing compound is also not critical, but is generally between about 100 to 1500 ppm by volume relative to the total mixture volume. Preferably, NF3 is the fluorine-containing compound, and a temperature greater than about 700 DEG C at a concentration of between about 100 to 1000 ppm is used.

公开(公告)号：DE3885637D1

公开(公告)日：1993-12-23

申请号：DE3885637

申请日：1988-03-08

Applicant: IBM

Inventor： LASKY JEROME BRETT

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/764 ,  H01L27/12

Abstract: The method comprises the steps of providing a layer of material on portions of the surface of a support structure; providing a polishing stop layer of substantially uniform thickness on different portions of the surface of said support structure, such that a first surface of said layer of material and a first surface of said polishing stop layer are substantially coplanar, said polishing stop layer being thinner than said layer of material; polishing the second surface of said layer of material to a point where a second surface of said polishing stop layer is encountered, such that the substantially uniform thickness of said polishing stop layer is used to define said layer of material to a layer of uniform thickness. In particular the method is used for forming improved silicon-on-insulator structures.

公开(公告)号：DE3686453D1

公开(公告)日：1992-09-24

申请号：DE3686453

申请日：1986-05-16

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN ,  SEDGWICK THOMAS OLIVER ,  STIFFLER SCOTT RICHARD

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/205 ,  H01L21/18 ,  H01L21/306

Abstract: A method of forming a thin silicon layer (12A) upon which semiconductor devices may be constructed. An epitaxial layer (12A, 12B) is grown on a silicon substrate (10), and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer (14) therein. An oxide layer (16A) is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer (100). The silicon substrate (10) is removed using grinding and/or HNA, the upper portions (12B) of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop (14) is removed using a non-selective etch. The remaining portion of the epitaxy (12A) forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

公开(公告)号：DE3571892D1

公开(公告)日：1989-08-31

申请号：DE3571892

申请日：1985-04-17

Applicant: IBM

Inventor： KINNEY WAYNE IRVING ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762

Abstract: A method is provided for forming semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions (30) and a set of surface regions (50) having characteristics which make them anodically etch slower than the remaining portion of the silicon body (10). These two sets of regions define portions (32, 52, 62) in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions (50) from each other and the remaining portion (62) of the silicon body. Typically in a P-type silicon body the buried and surface regions (30, 50) are N-type regions formed through ion implantation. Using these N-type regions to control the exposure of the P-type material to the anodic etching solution and the formation of the porous silicon regions, a structure is obtained wherein surface monocrystalline silicon regions are isolated from the rest of the silicon body by a uniform layer of silicon dioxide (62) having a predetermined thickness.

公开(公告)号：DE3871457D1

公开(公告)日：1992-07-02

申请号：DE3871457

申请日：1988-07-12

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  CRONIN JOHN EDWARD ,  LASKY JEROME BRETT

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L21/90

公开(公告)号：DE3584757D1

公开(公告)日：1992-01-09

申请号：DE3584757

申请日：1985-09-03

Applicant: IBM

Inventor： KINNEY WAYNE IRVING ,  KOBURGER CHARLES WILLIAM ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN ,  WHITE FRANCIS ROGER ,  TROUTMAN RONALD ROY

IPC: H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/82 ,  H01L21/00

Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells (26, 28) to each other and also of the field isolation doping regions (32, 10) to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks (30) for subsequent formation of the field-doping regions (32, 10); and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers (32, 10) self-aligned to the wells (26, 28) so that, with a subsequent masking step, oxide field isolations (36, 38) are defined over the doped oxide layers (32, 10). A heat cyde is then used to drive the field dopants into the corresponding field-doping regions (40, 42).

公开(公告)号：DE3576883D1

公开(公告)日：1990-05-03

申请号：DE3576883

申请日：1985-05-24

Applicant: IBM

Inventor： ABERNATHEY JOHN ROBERT ,  KINNEY WAYNE IRVING ,  LASKY JEROME BRETT ,  STIFFLER SCOTT RICHARD

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/00 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792 ,  H01L21/76

Abstract: A shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide (40). The bulk semiconductor (24) underlying the insulating layer (40) is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer (40) is defined into another FET with its drain region (60) above the gate oxide (40), whereby the drain region (60) also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.