公开(公告)号：DE1639262A1

公开(公告)日：1971-02-04

申请号：DE1639262

申请日：1968-01-05

Applicant: IBM

Inventor： PHILIP CASTRUCCI PAUL ,  HENRY COLLINS ROBERT ,  GEORGE SHEPHEARD ROBERT

IPC: H01L21/00 ,  H01L21/60 ,  H01L23/485 ,  H01L3/00

Abstract: 1,193,532. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 8 Jan., 1968 [13 Jan., 1967], No. 1001/68. Heading H1K. [Also in Division C7] Electrical contact is made to a semi-conductor region with an impurity concentration of at least 1018 atoms cm. -3 by depositing first a film of chromium, aluminium or titanium and then a film of nickel, silver, copper or copper chromium alloy. In one embodiment an antimony-doped N+type silicon wafer carrying an epitaxial N type layer is first provided with a silicon oxide coating by heating in dry oxygen and then in steam, or by R.F. sputtering, or with a layer of silicon nitride or alumina. Base and emitter regions are then formed by successive diffusions of boron and phosphorus into the N layer using standard planar techniques, the second diffusion doping the emitter and collector contact region with 5 Î 10 20 atoms/c.c. of phosphorus. Aluminium base and emitter contacts are next provided by vapour deposition overall followed by form-etching and sintering. Glass is subsequently deposited over the contacted face of the wafer in two stages of R.F. sputtering each followed by a firing stage. The wafer is then inverted in an evacuated vapour deposition chamber and its back collector contact face coated with successive layers of chromium, copper and gold of specified thickness while the wafer is held at 200-250‹ C. Holes are next etched through the glass layer to expose the aluminium contacts upon which similar layers of Cr, Cu and Au are then deposited through masks followed by layers of lead-tin solder by means of which nickel-plated copper balls are attached to the contacts. Finally the completed elements are attached to silver palladium lands on an alumina mounting plate and the ball contacts connected via nickel-plated copper strips to adjacent lands using lead-tin solder. In alternative planar diode and transistor embodiments the outer layer of gold is omitted.

公开(公告)号：DE1589935A1

公开(公告)日：1972-03-30

申请号：DE1589935

申请日：1967-03-25

Applicant: IBM

Inventor： AGUSTA BENJAMIN ,  HAROLD BARDELL PAUL ,  PHILIP CASTRUCCI PAUL ,  ATHANISUS HENLE ROBERT ,  PHILIP PECORARO RAYMOND

IPC: H01L27/08 ,  G11C11/411 ,  H03K3/286 ,  H03K3/288 ,  H01L19/00

Abstract: A monolithic integrated memory arrangement comprising, in combination, a plurality of individual memory cells, functionally isolated and electrically interconnected, in which each of said memory cells is object or corresponding to another memory cell mirroring mirror image, in vertical, horizontal and diagonal direction. (Machine-translation by Google Translate, not legally binding)

公开(公告)号：DE1914090A1

公开(公告)日：1969-10-09

申请号：DE1914090

申请日：1969-03-20

Applicant: IBM

Inventor： PHILIP CASTRUCCI PAUL ,  GEORGE GROCHOWSKI JUN EDWARD

IPC: C23C16/12 ,  H01L21/00 ,  H01L23/485 ,  C23C11/02

Abstract: 1,196,237. Contacting semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 18 March, 1969 [21 March, 1968], No. 14012/69. Heading H1K. [Also in Division C7] Aluminium ohmic contacts are formed on a silicon dioxide masked semi-conductor device (Si or Ge) by the disproportionation of an aluminium monohalide vapour, preferably the chloride. Aluminium trichloride vapour carried by an argon stream is passed over molten aluminium heated to above 900‹ C. and the monochloride vapour thus formed is passed over substrates heated to a temperature in the range 350-500‹ C. The deposition rate may be controlled by controlling the source temperature and/or the rate of flow of carrier gas. The apparatus described (Fig. 2, not shown) is a resistance heated batch furnace (though R.F. inductive heating could be used) in which regenerated aluminium trichloride is recovered from the walls at the cold end of the furnace. It is suggested that in a continuous process apparatus could be used in which the substrates pass slowly through a depositing zone.

公开(公告)号：DE1589975A1

公开(公告)日：1970-04-30

申请号：DE1589975

申请日：1967-10-26

Applicant: IBM

Inventor： PHILIP CASTRUCCI PAUL ,  WITT DAVID DE ,  ABHIMANYU DHAKA VIR ,  EDWARD MUTTER WALTER

IPC: H01L21/00 ,  H01L21/331 ,  H01L23/485 ,  H01L29/00 ,  H01L5/06

Abstract: 1,174,832. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 2 Oct., 1967 [27 Oct., 1966], No. 44711/67. Heading H1K. [Also in Division C7] A method of forming an elongated metal contact on a semi-conductor device comprises; (a) providing a protective coating, preferably of silicon dioxide or silicon nitride, on the semiconductor surface and forming at least one elongated aperture in the coating; (b) depositing a first layer of metal, preferably Pt, Pd or Mo, over the protective coating and the exposed semi-conductor surface to form an ohmic contact with the semi-conductor; (c) removing the metal from the protective coating; (d) depositing, e.g. by electroplating or by chemical or electroless deposition, a second layer of metal, preferably palladium, over the first layer within the aperture to increase the conductivity of the contact; and (e) depositing a third layer of metal over the protective coating to form an external hand pattern having an extension overlaying a portion only of the second layer. The third layer may consist of Al, Mo or a sandwich of Cu-Mo, Cr-Cu, Mo-Cu or Mo-Au.

公开(公告)号：DE1514010A1

公开(公告)日：1969-06-19

申请号：DEI0028041

申请日：1965-05-03

Applicant: IBM

Inventor： PHILIP CASTRUCCI PAUL

IPC: H01L23/485 ,  H01L29/00 ,  H01L29/06 ,  H01L29/40 ,  H03K3/26

Abstract: 1,103,184. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. 12 May, 1965 [27 May, 1964], No. 19980/65. Heading HlK. In a planar semi-conductor device a junction is covered with an insulating layer on top of which is located an electrode. The circuit of the device is arranged so that the insulated electrode is biased negatively with respect to the region in which an inversion layer forms. As shown, Fig. 6, a planar PNP transistor is produced with an electrode 62 overlying the oxide layer 16 over junction 14. A diode may be similarly constructed by omitting the emitter diffusion, Fig. 5 (not shown). Similar devices of opposite configuration (i.e. with the impurity types of their regions reversed) may also be constructed, e.g. the diode of Fig. 1 (not shown), and in this case the electrode over the oxide layer and the outer (or only) one of the electrodes contacting the semi-conductor may be combined, Figs. 3 and 4 (not shown). The diode of Fig. 1 (not shown), may be produced in an N-type silicon wafer, the surface of which is masked by thermally oxidation or by decomposition of an organic siloxane compound, by diffused-in boron to form a P-type region. The electrodes are deposited by evaporation or plating. The semi-conductor material may also be germanium or an intermetallic compound.

公开(公告)号：DE1764453A1

公开(公告)日：1971-07-22

申请号：DE1764453

申请日：1968-06-08

Applicant: IBM

Inventor： PHILIP CASTRUCCI PAUL ,  WESTLEY MASON JOHN

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L

Abstract: A method for fabricating dielectric isolated integrated devices which allows the formation of a truly planar surface. The method includes etching isolation channels in a semiconductor substrate through a suitable mask. The mask pattern is designed to enhance deeper etching at certain locations in the isolation channels. A dielectric layer is formed over the exposed surfaces of the isolation channels and a semiconductor material is grown in the channels. The deeper etched locations which are now filled with dielectric isolation are used as a depth guide in the formation of a dielectric layer from the semiconductor substrate surface opposite to the one from which the etching took place. The depth guide can be used in either a deep etch or lap-back process. The last isolation step is then to continue the dielectric layer past the depth guide to the major portion of the isolation channels to produce the fully isolated islands of semiconductor material in the semiconductor substrate.

公开(公告)号：DE1640470A1

公开(公告)日：1970-08-27

申请号：DE1640470

申请日：1966-06-23

Applicant: IBM

Inventor： PHILIP CASTRUCCI PAUL ,  SUNG-SOON IM SAMUEL

IPC: C23F1/02 ,  H01L21/00 ,  H01L23/29 ,  H01L23/485

Abstract: 1,084,003. Etching. INTERNATIONAL BUSINESS MACHINES CORPORATION June 7, 1966 [June 24, 1965], No. 25228/66. Heading B6J. [Also in Division H1] A method of forming an aperture in a layer of electrically insulating material (e.g. a layer of glass on a substrate of silicon semi-conductor material) comprises removing part of a metal layer formed on the insulating layer (e.g. a chromium layer overlaid by a copper layer, removed by etching after application, exposure and development of a photo-sensitive resist), forming a layer of masking material (e.g. silicon monoxide) on the remaining metal and the exposed surface of the insulating layer, removing the remaining metal and its overlying masking material to expose the insulating layer, and etching the exposed surface of the insulating layer. Chromium is removed with potassium ferricyanide and caustic soda. The silicon substrate can also be etched with silver nitrate, nitric acid and hydrofluoric acid.

公开(公告)号：DE1802849A1

公开(公告)日：1969-04-30

申请号：DE1802849

申请日：1968-10-12

Applicant: IBM

Inventor： GEORGE GROCHOWSKI EDWARD ,  FALLS WAPPINGER ,  PHILIP CASTRUCCI PAUL ,  STEVEN HESS MARTIN ,  MAHERAS GEORGE ,  DAVID NORTH WILLIAM

IPC: H01L21/822 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L27/00 ,  H01L27/04 ,  H01L29/04 ,  H01L29/73 ,  H01L7/64

Abstract: 1,241,057. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 2 Oct., 1968 [19 Oct., 1967], No. 46759/68. Heading H1K. A high conductivity N type zone in a device formed in a body of monocrystalline semiconductor material having a face parallel to a 100 crystallographic plane has a surface concentration of phosphorus of 2À5 to 4 x 10 3 parts per million by weight. This is achieved without significant precipitation of phosphorus due to the low dislocation density in thus aligned material. A junction isolated transistor (Fig. 2) in a typical solid circuit embodiment is formed on a 10-20 ohm. cm. P type silicon wafer 30 cut from a crystal grown along a 100 axis with its faces in a 100 plane. Subcollector region 32 is formed by diffusion and extends during epitaxial deposition of N-type epitaxial layer 34. A grid of isolation walls 37 is next diffused in prior to formation of base 38 and emitter 40 by successive diffusions. Alternatively region 32 is formed by ion implantation or etch and refill steps. Aluminium, platinum or palladium contacts 42 are formed by vapour deposition overall followed by pattern etching in a nitric-phosphoric acid mix. The diffusions are all effected through holes formed by conventional photolithographic techniques in thermal oxide layers. Arsenic is the dopant in regions 32, 34, boron in 37, 38 and phosphorus in the collector. The decline in current gain # with falling collector current is far less than in an otherwise identical device formed on a 111 orientated substrate. Manufacture of an oxide or nitride passivated planar epitaxial transistor (Fig. 1, not shown) with a phosphorus doped emitter and of an enhancement mode IGFET with N+ phosphorus doped source and drain regions is also described. The IGFET has a lower threshold voltage than its 111 orientated counterpart.