公开(公告)号：JP2003142483A

公开(公告)日：2003-05-16

申请号：JP2002212018

申请日：2002-07-22

Applicant: IBM

Inventor： GOUSEV EVGENI ,  AJMERA ATUL C ,  D EMIC CHRISTOPHER P

IPC: H01L21/318 ,  H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming an extremely thin gate dielectric for an integrated circuit device. SOLUTION: This method comprises steps of forming a nitride layer on a substrate by heating a silicon substrate 200 for a short time in the presence of an ammonia gas and reoxidizing the nitride layer to form an oxynitride layer 204 by heating the nitride layer for a short time in the presence of an nitrogen oxide gas. The oxynitride layer has nitrogen concentration of about 1.0×10 atoms/cm to about 6.0×10 atoms/cm , and a thickness limited in the range of less than 10 Å. The step of forming the nitride layer includes a step of heating a substrate for a short time in the presence of an ammonia gas with a temperature of about 650-1,000 deg.C and pressure of about 7.50×10 Pa to about 5.70 Pa. The step of reoxidizing the nitride layer includes a step of heating the nitride layer for a short time in the presence of a nitrogen oxide gas with a temperature of about 650-1,000 deg.C and pressure of about 7.50×10 Pa to about 5.70 Pa.

公开(公告)号：JP2002261278A

公开(公告)日：2002-09-13

申请号：JP2002004187

申请日：2002-01-11

Applicant: IBM

Inventor： AJMERA ATUL C ,  FUNG KA HING ,  KU VICTOR ,  SCHEPIS DOMINIC J

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for reducing overlapping capaci tance between a gate and source/drain in a MOSFET element. SOLUTION: A notched gate MOS element includes an encapsulated low- permittivity material or capsuled air or vacuum on the bottom of the notched gate. Capacitance loss is reduced greatly on the part due to low permittivity on an interface between the gate and the source/drain.

公开(公告)号：JP2005123597A

公开(公告)日：2005-05-12

申请号：JP2004271982

申请日：2004-09-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AJMERA ATUL C ,  BRYANT ANDRES ,  GILBERT PERCY V ,  GRIBELYUK MICHAEL A ,  MACIEJEWSKI EDWARD P ,  MO RENEE T ,  NARASIMHA SHREESH

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a gate electrode that avoids dielectric layer undercut during a silicide precleaning step. SOLUTION: A patterned gate stack includes a gate dielectric below a conductor having vertical sidewalls, and a dielectric layer is formed over the patterned gate stack and substrate surfaces. Nitride spacers are formed overlying the dielectric layer at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample and subsequently removed by an etch process such that only a portion of the nitride film ("plug") remains. The plug seals and encapsulates the dielectric layer underlying the each spacer, thus preventing the dielectric material from being undercut during the subsequent silicide precleaning process. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在硅化物预清洗步骤期间形成避免电介质层底切的栅电极的方法。 解决方案：图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，并且在图案化的栅极堆叠和衬底表面上形成介电层。 在每个垂直侧壁处形成覆盖电介质层的氮化物间隔物。 使用蚀刻工艺去除衬底表面上的电介质层，使得每个间隔物下面的电介质层的一部分保留。 然后，在整个样品上沉积氮化物层，然后通过蚀刻工艺去除，使得只有一部分氮化膜（“插塞”）保留。 塞子密封并封装每个间隔物下面的电介质层，从而防止在随后的硅化物预清洗过程中电介质材料被切下。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH11135454A

公开(公告)日：1999-05-21

申请号：JP23405098

申请日：1998-08-20

Applicant: IBM ,  SIEMENS AG

Inventor： AJMERA ATUL C ,  DEHM CHRISTINE ,  DOMENICUCCI ANTHONY G ,  GIFFORD GEORGE G ,  LOH STEPHEN K ,  PARKS CHRISTOPHER ,  SARDESAI VIRAJI Y

IPC: H01L21/28 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for forming a metallic silicide conductor in an integrated circuit. SOLUTION: A porous barrier is formed to prevent the thermal movement of silicon by enriching the grain boundary of a polysilicon layer 25 with nitrogen without forming an individual barrier layer. A reduction in the movement of the silicon prevents the agglomeration of the silicon in a metallic silicide layer formed on a policide gate/interconnection structure. The aggromelation of the silicon is a precedent advance phenomenon of a polycide inversion and hence effectively eliminates the polycide inversion passing through a lower oxide and damaging a device.

公开(公告)号：JP2002343883A

公开(公告)日：2002-11-29

申请号：JP2002096272

申请日：2002-03-29

Applicant: IBM

Inventor： PARK HEEMYONG ,  ASSADERAGHI FARIBORZ ,  AJMERA ATUL C ,  SHAHIDI GHAVAM G

IPC: H01L29/41 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a CMOS structure and a method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. SOLUTION: In this method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both the SOI and BOX interfaces. This sacrificial oxidation allows oxide spacer formation for gate-to-source/drain isolation, which enables raised source/drain fabrication without increasing contact resistance.

公开(公告)号：JPH1050700A

公开(公告)日：1998-02-20

申请号：JP13459897

申请日：1997-05-26

Applicant: IBM

Inventor： AJMERA ATUL C ,  GAMBINO JEFFREY P ,  NGUYEN SON VAN

IPC: H01L21/768 ,  C23C16/40 ,  H01L21/3105 ,  H01L21/316 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To improve the pore-filling characteristic by depositing a doped thin boron phosphide silicate glass film on a semiconductor substrate and annealing this film to finally deposit a thin phase boron phosphide silicate glass film. SOLUTION: A gate oxide layer 12 is deposited on a substrate, a polysilicon- silicon oxide layer 14 and Si layer 16 are formed on the layer 12, a thin film layer 20 is formed on the surfaces of the layers 14, 16, and a boron phosphide silicate glass layer 22 is deposited on this layer 20 and annealed, finally form a thin phase boron phosphide silicate glass layer 22. Thus it is possible to provide a good pore-filling characteristic and hold a capability of gettering such moving ions.

公开(公告)号：SG132642A1

公开(公告)日：2007-06-28

申请号：SG2006081384

申请日：2006-11-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： LUO ZHIJIONG ,  TEH YOUNG WAY ,  AJMERA ATUL C

Abstract: A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer (16) on each side of a gate region (14) of a substrate (12) and embedding the L-shaped spacers (16) in an oxide layer (28) so that the oxide layer (28) extends over a portion of the substrate a predetermined distance from a lateral edge of the L-shaped spacer (16). In one embodiment, the method further includes the step of removing oxide layers to expose the L-shape spacers.

公开(公告)号：DE69836117T2

公开(公告)日：2007-04-19

申请号：DE69836117

申请日：1998-07-28

Applicant: SIEMENS AG ,  IBM

Inventor： AJMERA ATUL C ,  DEHM CHRISTINE ,  DOMENICUCCI ANTHONY G ,  GIFFORD GEORGE G ,  LOH STEPHEN K ,  PARKS CHRISTOPHER ,  SARDESAI VIRAJI Y

IPC: H01L21/28 ,  H01L29/49

Abstract: A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided. The increased thermal stability of polycide structures and other structures including a body of polysilicon thus increases the heat budget that can be withstood by the structure and increases the manufacturing process window imposed by the presence of polysilicon which can be exploited in other processes such as annealing to develop a low resistance phase of refractory metal silicide included in the polycide structure, drive-in annealing for formation of source/drain regions of field effect transistors and the like.

公开(公告)号：DE69836117D1

公开(公告)日：2006-11-23

申请号：DE69836117

申请日：1998-07-28

Applicant: SIEMENS AG ,  IBM

Inventor： AJMERA ATUL C ,  DEHM CHRISTINE ,  DOMENICUCCI ANTHONY G ,  GIFFORD GEORGE G ,  LOH STEPHEN K ,  PARKS CHRISTOPHER ,  SARDESAI VIRAJI Y

IPC: H01L21/28 ,  H01L29/49

Abstract: A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided. The increased thermal stability of polycide structures and other structures including a body of polysilicon thus increases the heat budget that can be withstood by the structure and increases the manufacturing process window imposed by the presence of polysilicon which can be exploited in other processes such as annealing to develop a low resistance phase of refractory metal silicide included in the polycide structure, drive-in annealing for formation of source/drain regions of field effect transistors and the like.