公开(公告)号：EP1540276A4

公开(公告)日：2006-08-23

申请号：EP03793095

申请日：2003-08-15

Applicant: HYPERNEX INC ,  IBM

Inventor： KOZACZEK KRZYSZTOF J ,  KURTZ DAVID S ,  MORAN PAUL R ,  MARTIN ROGER I ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  MALHOTRA SANDRA G

IPC: G01B15/02 ,  G01N23/20 ,  G01N23/223

CPC classification number: G01N23/20 ,  G01B15/02

Abstract: An apparatus and method for mapping film thickness of one or more textured polycrystalline thin films. Multiple sample films of known thickness are provided. Each sample film is irradiated by x-ray at a measurement point to generate a diffraction image that captures a plurality of diffraction arcs. Texture information (i.e., pole densities) of the sample film is calculated based on incomplete pole figures collected on the diffraction image and used to correct the x-ray diffraction intensities from such sample. The corrected diffraction intensities are integrated for each sample film, and then used for constructing a calibration curve that correlates diffraction intensities with respective known film thickness of the sample films. The film thickness of a textured polycrystalline thin film of unknown thickness can therefore be mapped on such calibration curve, using a corrected and integrated diffraction intensity obtained for such thin film of unknown thickness.

公开(公告)号：JPH10308362A

公开(公告)日：1998-11-17

申请号：JP11245598

申请日：1998-04-22

Applicant: IBM ,  TOSHIBA CORP

Inventor： USUI TAKAMASA ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  FILIPPI RONALD G

IPC: C23C14/14 ,  C23C16/06 ,  C23C28/02 ,  H01L21/28 ,  H01L21/285

Abstract: PROBLEM TO BE SOLVED: To provide a metallization structure, which is small in resistivity, has excellent electricity transfer characteristics and at the same time, is textured to a high degree, and moreover, to prevent the formation of a hillock on the structure by a method wherein aluminium layers, aluminium alloy layers or both layers of the aluminium layers and the aluminum alloy layers, which come into contact electrically with tower group IVA metal layers having a thickness in a specified range, are formed. SOLUTION: Four or five-layer interconnected metallized layers are formed on interlayer stud connection layers 10, which are encircled with an insulator 8 and are connected with a silicon substratelike device substrate 6. Lower group IVA metal layers 13 consist of a titanium layer and the thickness of a metallization structure is about 90 to about 110 angstroms. By limiting this thickness, the structure of a metal layer, which is added afterwards, and the texture of the metal layer are controlled. Layers 15 to come into contact electrically with the lower layers 13 are aluminium layers or aluminium alloy layers. Titanium nitride layers 14 on the lower layers 13 prevent a reaction of the aluminium layers 15 with the lower layers 13 and capping layers consisting of titanium layers 18 and titanium nitride layers 19 perform an antireflection action.

公开(公告)号：JP2000091271A

公开(公告)日：2000-03-31

申请号：JP14860499

申请日：1999-05-27

Applicant: IBM

Inventor： DEHAVEN PATRICK W ,  GOLDSMITH CHARLES C ,  HURD JEFFERY L ,  SAAYANARAYANA KAJA ,  MICHAEL S REGARE ,  FRED D PERFECT

IPC: H01L21/28 ,  C25D5/50 ,  C25D7/00 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/52 ,  H05K1/09 ,  H05K3/22

Abstract: PROBLEM TO BE SOLVED: To obtain a method for manufacturing an electronic circuit by controlling growth of particle structures of a thin film after deposited on a substrate. SOLUTION: The present invention provides a method for depositingly forming a metallic thin film having different micro-structures on a substrate. The method, which controls particle growth in the micro-structures, includes steps of (a) depositingly forming the metallic thin film having the micro- structures of fine particles on the substrate, and (b) heating the metallic thin film at 70-100 deg.C for at least 5 minutes to change the fine particle micro- structures to stable micro-structures of large particles. A result of X-ray diffraction of an electroplated copper thin film having micro-structures of large particles is illustrated.

公开(公告)号：WO2004018959A3

公开(公告)日：2004-10-07

申请号：PCT/US0325769

申请日：2003-08-15

Applicant: HYPERNEX INC ,  IBM

Inventor： KOZACZEK KRZYSZTOF J ,  KURTZ DAVID S ,  MORAN PAUL R ,  MARTIN ROGER I ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  MALHOTRA SANDRA G

IPC: G01B15/02 ,  G01N23/20 ,  G01N23/223

CPC classification number: G01N23/20 ,  G01B15/02

Abstract: An apparatus and method for mapping film thickness of one or more textured polycrystalline thin films. Multiple sample films of known thickness are provided. Each sample film is irradiated by x-ray at a measurement point to generate a diffraction image that captures a plurality of diffraction arcs. Texture information (i.e., pole densities) of the sample film is calculated based on incomplete pole figures collected on the diffraction image and used to correct the x-ray diffraction intensities from such sample. The corrected diffraction intensities are integrated for each sample film, and then used for constructing a calibration curve that correlates diffraction intensities with respective known film thickness of the sample films. The film thickness of a textured polycrystalline thin film of unknown thickness can therefore be mapped on such calibration curve, using a corrected and integrated diffraction intensity obtained for such thin film of unknown thickness.

Abstract translation: 一种用于映射一个或多个纹理化多晶薄膜的膜厚度的装置和方法。 提供了已知厚度的多个样品膜。 每个样品膜在测量点用X射线照射以产生捕获多个衍射弧的衍射图像。 基于在衍射图像上收集的不完整极点图来计算样品膜的纹理信息（即极密度）并且用于校正来自该样品的x射线衍射强度。 校正的衍射强度对每个样品膜进行积分，然后用于构建使衍射强度与样品膜的相应已知膜厚相关的校准曲线。 因此，使用针对这种未知厚度的薄膜获得的校正和积分衍射强度，可以将具有未知厚度的纹理化多晶薄膜的膜厚度映射到这种校准曲线上。

公开(公告)号：JP2003309308A

公开(公告)日：2003-10-31

申请号：JP2003062285

申请日：2003-03-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： DEHAVEN PATRICK W ,  MEDEIROS DAVID R ,  MITZI DAVID B

IPC: H01L51/05 ,  C23C2/00 ,  H01L21/00 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/30 ,  H01L51/40

CPC classification number: H01L51/0003 ,  H01L51/0002 ,  H01L51/0025 ,  H01L51/0077 ,  H01L51/0512 ,  Y10T428/1471

Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive organic/inorganic hybrid material for melting processing which can be used for various use, including a light emission layer and a charge transfer layer of a flat panel display, a non-linear light/ photoconductive device, a chemical sensor, and an organic/inorganic light emitting diode, and a channel layer of an organic/inorganic thin film transistor and an organic/inorganic field-effect transistor. SOLUTION: The method, which is for manufacturing the organic/inorganic hybrid material for melting processing and which contains a step for maintaining the solid organic/inorganic hybrid material, at a temperature higher than the melting point of the organic/inorganic hybrid material but lower than its decomposition temperature, for a period of time sufficient to form a uniformly melt article and the step after that which cools down the uniformly melt article at ambient temperature, with sufficient conditions to generate the organic/ inorganic hybrid material for melting processing, is provided. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：为了提供可用于各种用途的廉价有机/无机混合材料用于熔融加工，包括平板显示器的发光层和电荷转移层，非线性光/ 光电导装置，化学传感器和有机/无机发光二极管，以及有机/无机薄膜晶体管和有机/无机场效应晶体管的沟道层。 解决方案：在高于有机/无机混合物的熔点的温度下，制造用于熔融加工的有机/无机混合材料的方法，其含有保持固体有机/无机混合材料的步骤 材料，但低于其分解温度，持续一段时间足以形成均匀熔化的制品，以及随后的步骤，其在环境温度下冷却均匀熔融制品，具有足够的条件以产生用于熔融加工的有机/无机混合材料 ，被提供。 版权所有（C）2004，JPO

公开(公告)号：JPH10308363A

公开(公告)日：1998-11-17

申请号：JP11252698

申请日：1998-04-22

Applicant: IBM ,  TOSHIBA CORP

Inventor： USUI TAKAMASA ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  FILIPPI RONALD G ,  YANG CHI-HUA ,  KATADA TOMIO ,  AOCHI HIDEAKI

IPC: C23C14/14 ,  C23C14/34 ,  C23C16/06 ,  C23C28/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a manufacture of a metalization structure having a superior electrical mobility, highly textured, and suitable for electrical connection or wiring. SOLUTION: The manufacture of a metalization structure comprises depositing a first lower layer 13 made of IVA family metal such as titan and having a thickness of approximately 90 Å to 110 Å on a substrate and after which, electrical depositing a layer made of at least one element selected from a group consisting of aluminum and aluminum alloy deposited on the layer 13 in such a way as to be in ohmic contact with the layer 13.

公开(公告)号：AU2003265462A8

公开(公告)日：2004-03-11

申请号：AU2003265462

申请日：2003-08-15

Applicant: IBM ,  HYPERNEX INC

Inventor： KOZACZEK KRZYSZTOF J ,  KURTZ DAVID S ,  MORAN PAUL R ,  MARTIN ROGER I ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  MALHOTRA SANDRA G

IPC: G01B15/02 ,  G01N23/20

公开(公告)号：DE102004016700A1

公开(公告)日：2004-11-18

申请号：DE102004016700

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEHAVEN PATRICK W ,  AGNELLO PAUL D ,  WONG KEITH KWONG HON ,  HUANG HSIANG-JEN ,  MURPHY RICHARD J ,  DZIOBKOWSKI CHET ,  CLEVENGER LAWRENCE ,  LAVOIE CHRISTIAN ,  ROVEDO NIVO ,  FANG SUNFEI

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.