公开(公告)号：JPH113952A

公开(公告)日：1999-01-06

申请号：JP10075098

申请日：1998-04-13

Applicant: IBM

Inventor： EDWARDS DAVID LINN ,  CAMMARANO ARMANDO SALVATORE ,  COFFIN JEFFREY THOMAS ,  COURTNEY MARK GERARD ,  DROFITZ STEPHEN S JR ,  ELLSWORTH MICHAEL JOSEPH JR ,  GOLDMANN LEWIS SIGMUND ,  IRUVANTI SUSHUMNA ,  POMPEO FRANK L ,  SABLINSKI WILLIAM EDWARD ,  SHERIF RAED A ,  TOY HILTON T

IPC: B23K35/14 ,  B23K35/26 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02 ,  H01L23/10

Abstract: PROBLEM TO BE SOLVED: To enable a solder sealed band to apply to an inequality with a large expansion between a cover and a substrate by a method wherein the solder sealed band is formed, by laminating first and second solder interconnect layers and a high-melting point solder core holding the solder core between the first and the second solder interconnect layers. SOLUTION: A solder sealed band is formed into a structure, wherein a first solder interconnect layer 41 is provided on the surface on one side of the surfaces of a high-melting point solder core 43 and at the same time, a second solder interconnect layer 45 is provided on the other surface of the core 43 to make lower the melting point of the layer 41 than that of the layer 45, and, moreover, the melting points of the layers 41 and 45 are made lower than that of the core 43. As a result, the band can apply to an inequality with a large expansion between a cover 20 under use and a substrate 10, it becomes possible to maintain the reliability of a hermetic sealing of the band, and the reprocessable degree of the band and the thermal performance of a package can be modified.

公开(公告)号：MY120319A

公开(公告)日：2005-10-31

申请号：MYPI9801534

申请日：1998-04-06

Applicant: IBM

Inventor： EDWARDS DAVID LINN ,  SHERIF RAED A ,  TOY HILTON T ,  DROFITZ STEPHEN S JR ,  CAMMARANO ARMANDO SALVATORE ,  COFFIN JEFFREY THOMAS ,  COURTNEY MARK GERARD ,  ELLSWORTH MICHAEL JOSEPH JR ,  GOLDMANN LEWIS SIGMUND ,  IRUVANTI SUSHUMNA ,  POMPEO FRANK LOUIS ,  SABLINSKI WILLIAM EDWARD

IPC: B23K31/02 ,  B23K35/14 ,  B23K35/22 ,  B23K35/26 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02 ,  H01L23/10

Abstract: THE PRESENT INVENTION RELATES GENERALLY TO A NEW SCHEME OF PROVIDING A SEAL BAND FOR SEMICONDUCTOR SUBSTRATES AND CHIP CARRIERS. MORE PARTICULARLY, THE INVENTION ENCOMPASSES A STRUCTURE AND A METHOD THAT USES A MULTI-LAYER METALLIC SEAL (23) TO PROVIDE PROTECTION TO CHIPS ON A CHIP CARRIER. THIS MULTI-LAYER METAL SEAL PROVIDES BOTH ENHANCED HERMETICITY LIFETIME AND ENVIRONMENTAL PROTECTION. FOR THE PREFERRED EMBODIMENT THE MULTI-LAYER METALLIC SEAL BAND IS A THREE LAYER, SOLDER SANDWICH STRUCTURE WHICH IS USED TO CREATE A LOW COST, HIGH RELIABILITY, HERMETIC SEAL FOR THE MODULE. THIS SOLDER SANDWICH HAS A HIGH MELTING TEMPERATURE THICK SOLDER INNER CORE (43), AND LOWER MELTING POINT THIN INTERCONNECTING SOLDER LAYERS (41, 45), WHERE THE THIN INTERCONNECTING SOLDER LAYERS MAY HAVE SIMILAR OR DIFFERENT MELTING POINTS. (FIGURE 3)

公开(公告)号：SG63843A1

公开(公告)日：1999-03-30

申请号：SG1998000886

申请日：1998-04-28

Applicant: IBM

Inventor： EDWARDS DAVID LINN ,  CAMMARANO ARMANDO SALVATORE ,  COFFIN JEFFERY THOMAS ,  COURTNEY MARK GERARD ,  DROFITZ STEPHEN S JR ,  ELLSWORTH MICHAEL JOSEPH JR ,  GOLDMANN LEWIS SIGMUND ,  IRUVANTI SUSHUMNA ,  SABLINSKI WILLIAM EDWARD ,  SHERIE RAED A ,  TOY HILTON T ,  POMPEO FRANK LOUIS

IPC: B23K35/14 ,  B23K35/26 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02 ,  H01L23/10 ,  H05K3/34

Abstract: A scheme of providing a seal band for semi-conductor substrates and chip carriers encompasses a structure and a method that uses a multi-layer metallic seal (23) to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection. For the preferred embodiment the multi-layer metallic seal band is a three layer, solder sandwich structure which is used to create a low cost, high reliability. hermetic seal for the module. This solder sandwich has a high melting temperature thick solder inner core (43), and lower melting point thin interconnecting solder layers (41.45). where the thin interconnecting solder layers may have similar or different melting points.

公开(公告)号：CA1124324A

公开(公告)日：1982-05-25

申请号：CA345148

申请日：1980-02-06

Applicant: IBM

Inventor： CAMMARANO ARMANDO S ,  DIGIACOMO GIULIO ,  DROFITZ STEPHEN S JR

IPC: G01R19/00 ,  G01R19/08 ,  G01R19/15 ,  G01R31/302 ,  H01L21/66

Abstract: A method for determining the paths of current flow in an irregularly shaped conductor. A metal is plated onto a substrate in the desired geometric pattern. The metal is then brought to within about 4 percent of its melting point and a current is put through it. After an amount of time that depends upon the temperature and current utilized, there will have been a mass migration in the metal resulting in a corrugated surface having ridges and valleys that are parallel to the current flow. The ridges and valleys may be observed optically or by scanning electron microscope. PO9-79-009