公开(公告)号：WO03012867A2

公开(公告)日：2003-02-13

申请号：PCT/GB0203436

申请日：2002-07-26

Applicant: IBM ,  IBM UK

Inventor： ALCOE DAVID JAMES ,  COFFIN JEFFREY THOMAS ,  GAYNES MICHAEL ANTHONY ,  HAMEL HARVEY CHARLES ,  INTERRANTE MARIO ,  PETERSON BRENDA LEE ,  SHANNON MEGAN ,  SABLINSKI WILLIAM EDWARD ,  SPRING CHRISTOPHER TODD ,  STUTZMAN RANDALL JOSEPH ,  WEISMAN RENEE ,  ZITZ JEFFREY ALLEN

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/552 ,  H05K9/00 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01087 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3025 ,  H01L2924/00

Abstract: Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.

Abstract translation: 结合有EMI屏蔽的电子封装，特别是包含嵌入有接地带的半导体芯片载体结构的半导体器件，其适于减少用于高速开关电子封装的输出和事件EMI发射。

公开(公告)号：EP1545826A4

公开(公告)日：2009-02-11

申请号：EP03755830

申请日：2003-09-12

Applicant: IBM

Inventor： INTERRANTE MARIO ,  FARCOOQ MUKTA G ,  SABLINSKI WILLIAM EDWARD

IPC: B23K1/00 ,  B23K31/02 ,  B23K35/12 ,  B23K35/14 ,  B23K35/26 ,  B23K35/34 ,  B23K101/40 ,  B23K101/42 ,  C22C13/00 ,  H05K3/34

CPC classification number: B23K1/0016 ,  B23K35/262 ,  B23K2201/36 ,  H01L2224/16225 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613

Abstract: A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module (20) to a circuit board (120). An off-eutectic solder (60) concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder (60) contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition (60) provides an inter­metallic phase structure in the module side fillet during assembly. The inter­metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns (100) from the board (120) without simultaneous removal from the module (20).

公开(公告)号：JPH113952A

公开(公告)日：1999-01-06

申请号：JP10075098

申请日：1998-04-13

Applicant: IBM

Inventor： EDWARDS DAVID LINN ,  CAMMARANO ARMANDO SALVATORE ,  COFFIN JEFFREY THOMAS ,  COURTNEY MARK GERARD ,  DROFITZ STEPHEN S JR ,  ELLSWORTH MICHAEL JOSEPH JR ,  GOLDMANN LEWIS SIGMUND ,  IRUVANTI SUSHUMNA ,  POMPEO FRANK L ,  SABLINSKI WILLIAM EDWARD ,  SHERIF RAED A ,  TOY HILTON T

IPC: B23K35/14 ,  B23K35/26 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02 ,  H01L23/10

Abstract: PROBLEM TO BE SOLVED: To enable a solder sealed band to apply to an inequality with a large expansion between a cover and a substrate by a method wherein the solder sealed band is formed, by laminating first and second solder interconnect layers and a high-melting point solder core holding the solder core between the first and the second solder interconnect layers. SOLUTION: A solder sealed band is formed into a structure, wherein a first solder interconnect layer 41 is provided on the surface on one side of the surfaces of a high-melting point solder core 43 and at the same time, a second solder interconnect layer 45 is provided on the other surface of the core 43 to make lower the melting point of the layer 41 than that of the layer 45, and, moreover, the melting points of the layers 41 and 45 are made lower than that of the core 43. As a result, the band can apply to an inequality with a large expansion between a cover 20 under use and a substrate 10, it becomes possible to maintain the reliability of a hermetic sealing of the band, and the reprocessable degree of the band and the thermal performance of a package can be modified.

公开(公告)号：WO2004026517A3

公开(公告)日：2004-05-06

申请号：PCT/US0329092

申请日：2003-09-12

Applicant: IBM

Inventor： INTERRANTE MARIO ,  FARCOOQ MUKTA G ,  SABLINSKI WILLIAM EDWARD

IPC: B23K1/00 ,  B23K35/14 ,  B23K35/26 ,  B23K101/40 ,  B23K101/42 ,  C22C13/00 ,  H05K3/34 ,  B23K31/02 ,  B23K35/12 ,  B23K35/34

CPC classification number: B23K1/0016 ,  B23K35/262 ,  B23K2201/36 ,  H01L2224/16225 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613

Abstract: A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module (20) to a circuit board (120). An off-eutectic solder (60) concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder (60) contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition (60) provides an inter­metallic phase structure in the module side fillet during assembly. The inter­metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns (100) from the board (120) without simultaneous removal from the module (20).

Abstract translation: 用于电子元件的第二层焊接连接的无铅焊料层次结构，例如将电子模块（20）连接到电路板（120）。 SnCu或SnAg的非共晶焊料（60）浓度用于模块侧连接。 这种非共晶焊料（60）含有足够的金属间化合物以提供模块侧连接，并具有稳健的二级装配和返工工艺。 非共晶组合物（60）在组装期间在模块侧边角中提供金属间相结构。 金属间相结构消除了第二级组装期间的倾斜和塌陷问题，并且通过提供更加粘性的接头允许从板（120）移除柱（100）而无需同时从模块（20）移除而帮助返工。

公开(公告)号：MY126247A

公开(公告)日：2006-09-29

申请号：MYPI20022733

申请日：2002-07-18

Applicant: IBM

Inventor： ALCOE DAVID JANES ,  STUTZMAN RANDALL JOSEPH ,  WEISMAN RENEE L ,  ZITZ JEFFREY ALLEN ,  COFFIN JEFFREY THOMAS ,  GAYNES MICHAEL ANTHONY ,  HAMEL HARVEY CHARLES ,  INTERRANTE MARIO J ,  PETERSON BRENDA LEE ,  SHANNON MEGAN J ,  SABLINSKI WILLIAM EDWARD ,  SPRING CHRISTOPHER TODD

IPC: H01L23/29 ,  H01L23/552 ,  H01L23/31 ,  H05K9/00

Abstract: ELECTRONIC PACKAGES INCORPORATING EMI SHIELDING, AND PARTICULARLY SEMICONDUCTOR DEVICES WHICH INCORPORATED SEMICONDUCTOR CHIP-CARRIER STRUCTURES HAVING GROUNDED BANDS EMBEDDED THEREIN WHICH ARE ADAPTED TO REDUCE OUTGOING AND INCLUDENT EMI EMISSIONS FOR HIGH-SPEED SWITCHING ELECTRONIC PACKAGES. (FIG. 1)

公开(公告)号：PL374701A1

公开(公告)日：2005-10-31

申请号：PL37470103

申请日：2003-09-12

Applicant: IBM

Inventor： INTERRANTE MARIO ,  FAROOQ MUKTA G ,  SABLINSKI WILLIAM EDWARD

IPC: B23K1/00 ,  B23K35/14 ,  B23K35/26 ,  B23K101/40 ,  B23K101/42 ,  C22C13/00 ,  H05K3/34 ,  B23K31/02

Abstract: A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module to a circuit board. An off-eutectic solder concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition provides an inter-metallic phase structure in the module side fillet during assembly. The inter-metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns from the board without simultaneous removal from the module.

公开(公告)号：DE69832324D1

公开(公告)日：2005-12-22

申请号：DE69832324

申请日：1998-04-14

Applicant: IBM

Inventor： EDWARDS DAVID LINN ,  CAMMARANO ARMANDO SALVATORE ,  COFFIN JEFFREY THOMAS ,  COURTNEY MARK GERARD ,  DROFITZ JR ,  ELLSWORTH JR ,  GOLDMANN LEWIS SIGMUND ,  IRUVANTI SUSHUMNA ,  POMPEO FRANK LOUIS ,  SABLINSKI WILLIAM EDWARD ,  SHERIF RAED A ,  TOY HILTON T

IPC: B23K35/14 ,  B23K35/26 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02 ,  H01L23/10

Abstract: A scheme of providing a seal band for semi-conductor substrates and chip carriers encompasses a structure and a method that uses a multi-layer metallic seal (23) to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection. For the preferred embodiment the multi-layer metallic seal band is a three layer, solder sandwich structure which is used to create a low cost, high reliability. hermetic seal for the module. This solder sandwich has a high melting temperature thick solder inner core (43), and lower melting point thin interconnecting solder layers (41.45). where the thin interconnecting solder layers may have similar or different melting points.

公开(公告)号：HU0401737A2

公开(公告)日：2004-12-28

申请号：HU0401737

申请日：2002-07-26

Applicant: IBM

Inventor： ALCOE DAVID JAMES ,  COFFIN JEFFREY THOMAS ,  GAYNES MICHAEL ANTHONY ,  HAMEL HARVEY CHARLES ,  INTERRANTE MARIO ,  PETERSON BRENDA LEE ,  SHANNON MEGAN ,  SABLINSKI WILLIAM EDWARD ,  SPRING CHRISTOPHER TODD ,  STUTZMAN RANDALL JOSEPH ,  WEISMAN RENEE ,  ZITZ JEFFREY ALLEN

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/552 ,  H05K9/00 ,  H01L23/66

Abstract: Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.

公开(公告)号：AU2003273330A1

公开(公告)日：2004-04-08

申请号：AU2003273330

申请日：2003-09-12

Applicant: IBM

Inventor： FARCOOQ MUKTA G ,  SABLINSKI WILLIAM EDWARD ,  INTERRANTE MARIO

IPC: B23K1/00 ,  B23K35/14 ,  B23K35/26 ,  B23K101/40 ,  B23K101/42 ,  C22C13/00 ,  H05K3/34

Abstract: A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module to a circuit board. An off-eutectic solder concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition provides an inter-metallic phase structure in the module side fillet during assembly. The inter-metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns from the board without simultaneous removal from the module.

公开(公告)号：DE69832324T2

公开(公告)日：2006-07-27

申请号：DE69832324

申请日：1998-04-14

Applicant: IBM

Inventor： EDWARDS DAVID LINN ,  CAMMARANO ARMANDO SALVATORE ,  COFFIN JEFFREY THOMAS ,  COURTNEY MARK GERARD ,  DROFITZ STEPHEN S ,  ELLSWORTH MICHAEL JOSEPH ,  GOLDMANN LEWIS SIGMUND ,  IRUVANTI SUSHUMNA ,  POMPEO FRANK LOUIS ,  SABLINSKI WILLIAM EDWARD ,  SHERIF RAED A ,  TOY HILTON T

IPC: B23K35/14 ,  H01L23/10 ,  B23K35/26 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02

Abstract: A scheme of providing a seal band for semi-conductor substrates and chip carriers encompasses a structure and a method that uses a multi-layer metallic seal (23) to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection. For the preferred embodiment the multi-layer metallic seal band is a three layer, solder sandwich structure which is used to create a low cost, high reliability. hermetic seal for the module. This solder sandwich has a high melting temperature thick solder inner core (43), and lower melting point thin interconnecting solder layers (41.45). where the thin interconnecting solder layers may have similar or different melting points.