公开(公告)号：JP2000208654A

公开(公告)日：2000-07-28

申请号：JP37350899

申请日：1999-12-28

Applicant: IBM

Inventor： TROY HILTON T ,  SHERIF RAED A

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/42

Abstract: PROBLEM TO BE SOLVED: To improve thermal performance of an electronic module package designed for an electric power level by providing a shorter heat-transfer path between a chip device and a module lid, using a direct thermal gap method. SOLUTION: A thermally conductive flat lid 20 is provided on a chip 16, while contacting a paste thermally. The lid 20, spreading in horizontal direction wider than the chip, suspends a male-lid seal ring 43 along the perimeter of the lid 10 from the part of the lid 20 overhanging the chip. A corresponding female-slot is provided on a substrate 41. The female-slot has a sidewall, and a sealant is provided in the slot, forming a sealing part 44 between the side wall of slot and a hanging male seal ring 43. With a compliant thermal interface which uses a thermal paste provided between a chip device 16 and the lid 20, a slot as a variable-height seal joint is used to reduce/control the fluctuation and tolerance of the thermal gap of a sealed module.

公开(公告)号：JPH113952A

公开(公告)日：1999-01-06

申请号：JP10075098

申请日：1998-04-13

Applicant: IBM

Inventor： EDWARDS DAVID LINN ,  CAMMARANO ARMANDO SALVATORE ,  COFFIN JEFFREY THOMAS ,  COURTNEY MARK GERARD ,  DROFITZ STEPHEN S JR ,  ELLSWORTH MICHAEL JOSEPH JR ,  GOLDMANN LEWIS SIGMUND ,  IRUVANTI SUSHUMNA ,  POMPEO FRANK L ,  SABLINSKI WILLIAM EDWARD ,  SHERIF RAED A ,  TOY HILTON T

IPC: B23K35/14 ,  B23K35/26 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02 ,  H01L23/10

Abstract: PROBLEM TO BE SOLVED: To enable a solder sealed band to apply to an inequality with a large expansion between a cover and a substrate by a method wherein the solder sealed band is formed, by laminating first and second solder interconnect layers and a high-melting point solder core holding the solder core between the first and the second solder interconnect layers. SOLUTION: A solder sealed band is formed into a structure, wherein a first solder interconnect layer 41 is provided on the surface on one side of the surfaces of a high-melting point solder core 43 and at the same time, a second solder interconnect layer 45 is provided on the other surface of the core 43 to make lower the melting point of the layer 41 than that of the layer 45, and, moreover, the melting points of the layers 41 and 45 are made lower than that of the core 43. As a result, the band can apply to an inequality with a large expansion between a cover 20 under use and a substrate 10, it becomes possible to maintain the reliability of a hermetic sealing of the band, and the reprocessable degree of the band and the thermal performance of a package can be modified.

公开(公告)号：GB2345577B

公开(公告)日：2004-02-04

申请号：GB9930856

申请日：1999-12-24

Applicant: IBM

Inventor： TROY HILTON T ,  SHERIF RAED A

IPC: H01L23/10 ,  H01L23/02 ,  H01L23/42

Abstract: Tolerances in chip, substrate and hardware dimensions are accommodated by means of a floating sealing structure to insure that compliant thermally conductive paste disposed between the chip and its lid is as trim as possible in order to reduce thermal resistance of the paste so as to be able to run the chip at a cooler temperature. Standoffs are also preferably employed to insure proper paste gap thickness.

公开(公告)号：DE69832324D1

公开(公告)日：2005-12-22

申请号：DE69832324

申请日：1998-04-14

Applicant: IBM

Inventor： EDWARDS DAVID LINN ,  CAMMARANO ARMANDO SALVATORE ,  COFFIN JEFFREY THOMAS ,  COURTNEY MARK GERARD ,  DROFITZ JR ,  ELLSWORTH JR ,  GOLDMANN LEWIS SIGMUND ,  IRUVANTI SUSHUMNA ,  POMPEO FRANK LOUIS ,  SABLINSKI WILLIAM EDWARD ,  SHERIF RAED A ,  TOY HILTON T

IPC: B23K35/14 ,  B23K35/26 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02 ,  H01L23/10

Abstract: A scheme of providing a seal band for semi-conductor substrates and chip carriers encompasses a structure and a method that uses a multi-layer metallic seal (23) to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection. For the preferred embodiment the multi-layer metallic seal band is a three layer, solder sandwich structure which is used to create a low cost, high reliability. hermetic seal for the module. This solder sandwich has a high melting temperature thick solder inner core (43), and lower melting point thin interconnecting solder layers (41.45). where the thin interconnecting solder layers may have similar or different melting points.

公开(公告)号：GB2345577A

公开(公告)日：2000-07-12

申请号：GB9930856

申请日：1999-12-24

Applicant: IBM

Inventor： TROY HILTON T ,  SHERIF RAED A

IPC: H01L23/10 ,  H01L23/02 ,  H01L23/42

Abstract: Tolerances in chip, substrate and hardware dimensions are accommodated by a floating sealing structure to ensure that compliant thermally conductive paste 17 disposed between the chip and its lid is as trim as possible. Standoffs or spacers 21 are preferably employed to ensure proper paste gap thickness. The floating sealant structure between the lid 20 and the substrate 10 using sealants 41 and 42 may be achieved in a variety of depicted ways.

公开(公告)号：DE69832324T2

公开(公告)日：2006-07-27

申请号：DE69832324

申请日：1998-04-14

Applicant: IBM

Inventor： EDWARDS DAVID LINN ,  CAMMARANO ARMANDO SALVATORE ,  COFFIN JEFFREY THOMAS ,  COURTNEY MARK GERARD ,  DROFITZ STEPHEN S ,  ELLSWORTH MICHAEL JOSEPH ,  GOLDMANN LEWIS SIGMUND ,  IRUVANTI SUSHUMNA ,  POMPEO FRANK LOUIS ,  SABLINSKI WILLIAM EDWARD ,  SHERIF RAED A ,  TOY HILTON T

IPC: B23K35/14 ,  H01L23/10 ,  B23K35/26 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02

Abstract: A scheme of providing a seal band for semi-conductor substrates and chip carriers encompasses a structure and a method that uses a multi-layer metallic seal (23) to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection. For the preferred embodiment the multi-layer metallic seal band is a three layer, solder sandwich structure which is used to create a low cost, high reliability. hermetic seal for the module. This solder sandwich has a high melting temperature thick solder inner core (43), and lower melting point thin interconnecting solder layers (41.45). where the thin interconnecting solder layers may have similar or different melting points.

公开(公告)号：MY123232A

公开(公告)日：2006-05-31

申请号：MYPI9905470

申请日：1999-12-15

Applicant: IBM

Inventor： TROY HILTON T ,  SHERIF RAED A

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/12 ,  H01L23/42

Abstract: TOLERANCES IN CHIP, SUBSTRATE AND HARDWARE DIMENSIONS ARE ACCOMMODATED BY MEANS OF A FLOATING SEALING STRUCTURE TO INSURE THAT COMPLIANT THERMALLY CONDUCTIVE PASTE DISPOSED BETWEEN THE CHIP AND ITS LID IS AS TRIM AS POSSIBLE IN ORDER TO REDUCE THERMAL RESISTANCE OF THE PASTE SO AS TO BE ABLE TO RUN THE CHIP AT A COOLER TEMPERATURE. STANDOFFS ARE ALSO PREFERABLY EMPLOYED TO INSURE PROPER PASTE GAP THICKNESS.

公开(公告)号：MY120319A

公开(公告)日：2005-10-31

申请号：MYPI9801534

申请日：1998-04-06

Applicant: IBM

Inventor： EDWARDS DAVID LINN ,  SHERIF RAED A ,  TOY HILTON T ,  DROFITZ STEPHEN S JR ,  CAMMARANO ARMANDO SALVATORE ,  COFFIN JEFFREY THOMAS ,  COURTNEY MARK GERARD ,  ELLSWORTH MICHAEL JOSEPH JR ,  GOLDMANN LEWIS SIGMUND ,  IRUVANTI SUSHUMNA ,  POMPEO FRANK LOUIS ,  SABLINSKI WILLIAM EDWARD

IPC: B23K31/02 ,  B23K35/14 ,  B23K35/22 ,  B23K35/26 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02 ,  H01L23/10

Abstract: THE PRESENT INVENTION RELATES GENERALLY TO A NEW SCHEME OF PROVIDING A SEAL BAND FOR SEMICONDUCTOR SUBSTRATES AND CHIP CARRIERS. MORE PARTICULARLY, THE INVENTION ENCOMPASSES A STRUCTURE AND A METHOD THAT USES A MULTI-LAYER METALLIC SEAL (23) TO PROVIDE PROTECTION TO CHIPS ON A CHIP CARRIER. THIS MULTI-LAYER METAL SEAL PROVIDES BOTH ENHANCED HERMETICITY LIFETIME AND ENVIRONMENTAL PROTECTION. FOR THE PREFERRED EMBODIMENT THE MULTI-LAYER METALLIC SEAL BAND IS A THREE LAYER, SOLDER SANDWICH STRUCTURE WHICH IS USED TO CREATE A LOW COST, HIGH RELIABILITY, HERMETIC SEAL FOR THE MODULE. THIS SOLDER SANDWICH HAS A HIGH MELTING TEMPERATURE THICK SOLDER INNER CORE (43), AND LOWER MELTING POINT THIN INTERCONNECTING SOLDER LAYERS (41, 45), WHERE THE THIN INTERCONNECTING SOLDER LAYERS MAY HAVE SIMILAR OR DIFFERENT MELTING POINTS. (FIGURE 3)