公开(公告)号：DE3481148D1

公开(公告)日：1990-03-01

申请号：DE3481148

申请日：1984-11-30

Applicant: IBM

Inventor： GEIPEL HENRY JOHN JR ,  SCHAEFER CHARLES ANDREW ,  WHITE FRANCIS ROGER ,  WURSTHORN JOHN MICHAEL

IPC: H01L21/22 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/321 ,  H01L21/324 ,  H01L21/322

Abstract: A process is provided for fabricating a semiconductor structure wherein the structure has to be exposed to certain oxidizing conditions during certain of its processing steps, such as its high temperature annealing in an oxidizing ambient. It includes depositing a "sacrificial" layer, such as silicon, to provide a uniformly oxidizing surface during subsequent annealing operations. This sacrificial layer, which oxidizes uniformly, produces an oxide layer which also etches uniformly. Thus, after the annealing is completed, the surface oxide is removed through etching and the remaining sacrificial layer is then also removed through a different etching step.

公开(公告)号：DE69218076D1

公开(公告)日：1997-04-17

申请号：DE69218076

申请日：1992-08-10

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  FARRAR PAUL ALDEN ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  VAN DER HOEVEN WILLEM BERNARD ,  WHITE FRANCIS ROGER

IPC: H01L27/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

Abstract: A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip (50) having high aspect ratio metallized trenches (62) therein extending from a first surface to a second surface (58) thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate (52). Next the integrated circuit device is affixed to a carrier (70) such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches (66). Specific details of the fabrication method and the resultant multichip package are set forth.

公开(公告)号：DE3584757D1

公开(公告)日：1992-01-09

申请号：DE3584757

申请日：1985-09-03

Applicant: IBM

Inventor： KINNEY WAYNE IRVING ,  KOBURGER CHARLES WILLIAM ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN ,  WHITE FRANCIS ROGER ,  TROUTMAN RONALD ROY

IPC: H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/82 ,  H01L21/00

Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells (26, 28) to each other and also of the field isolation doping regions (32, 10) to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks (30) for subsequent formation of the field-doping regions (32, 10); and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers (32, 10) self-aligned to the wells (26, 28) so that, with a subsequent masking step, oxide field isolations (36, 38) are defined over the doped oxide layers (32, 10). A heat cyde is then used to drive the field dopants into the corresponding field-doping regions (40, 42).

公开(公告)号：DE69218076T2

公开(公告)日：1997-09-18

申请号：DE69218076

申请日：1992-08-10

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  FARRAR PAUL ALDEN ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  VAN DER HOEVEN WILLEM BERNARD ,  WHITE FRANCIS ROGER

IPC: H01L27/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

Abstract: A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip (50) having high aspect ratio metallized trenches (62) therein extending from a first surface to a second surface (58) thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate (52). Next the integrated circuit device is affixed to a carrier (70) such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches (66). Specific details of the fabrication method and the resultant multichip package are set forth.

公开(公告)号：DE3483659D1

公开(公告)日：1991-01-10

申请号：DE3483659

申请日：1984-05-16

Applicant: IBM

Inventor： ROBERTS STANLEY ,  WHITE FRANCIS ROGER

IPC: H01L29/78 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/768 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L21/31