公开(公告)号：JP2010283347A

公开(公告)日：2010-12-16

申请号：JP2010123865

申请日：2010-05-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOGAMI TAKESHI ,  EDELSTEIN DANIEL C ,  ROSSNAGEL STEPHEN M ,  FLAITZ PHILIP LEE ,  DEHAVEN PATRICK WILLIAM ,  YANG CHIH-CHAO

IPC: H01L21/3205 ,  H01L21/28 ,  H01L23/52

CPC classification number: H01L21/2855 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  Y10T428/24917

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of attaining high reliability and a high production yield by eliminating a void generation portion in a liner/copper interface. SOLUTION: The method of forming a diffusion barrier used for manufacturing the semiconductor device includes a step for depositing an iridium-doped tantalum-based barrier layer on a pattern-formed intermediate dielectric (ILD) layer by a physical vapor deposition (PVD) process, and the barrier layer is deposited to form the barrier layer into amorphous structure as a result, at least 60% of an iridium concentration in terms of atomic weight. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过消除衬里/铜界面中的空隙生成部分来制造能够获得高可靠性和高生产率的半导体器件的方法。 解决方案：形成用于制造半导体器件的扩散阻挡层的方法包括通过物理气相沉积（PVD）在形成图案的中间电介质（ILD）层上沉积铱掺杂的钽基阻挡层的步骤 ），并且阻挡层被沉积以形成无定形结构的阻挡层，至少60％的铱浓度以原子量计。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JPH10214886A

公开(公告)日：1998-08-11

申请号：JP874398

申请日：1998-01-20

Applicant: IBM ,  SIEMENS AG ,  TOSHIBA CORP

Inventor： BENEDICT JOHN PRESTON ,  DOBUZINSKY DAVID MARK ,  FLAITZ PHILIP LEE ,  HAMMERL ERWIN N ,  HO HERBERT ,  MOSEMAN JAMES F ,  PALM HERBERT ,  YOSHIDA SEIKO ,  TAKATO HIROSHI

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To form an effective O2 diffusion barrier by forming a conformal layer that is selected from a group consisting of a double layer that is made of oxide and nitride in a separation groove and on a protection layer, depositing a CVD layer consisting of an oxide-filling material on the layer, and releasing the protection layer and the conformal layer. SOLUTION: A conformal layer 20 with a thickness of approximately 5-15mm being selected from a group consisting of an acid nitride, a double layer consisting of oxide and nitride, and a double layer consisting of acid nitride and nitride is formed on a protection layer (a pad nitride layer 14 and a pad oxide layer 12) and a separation groove (thermal oxide liner) 18. Then, an oxide-filling material 22 such as tetraethylortosilicate with a thickness of 450-500nm is deposited by the CVD supported by ozone, and the oxide-filling material 22 is subjected to anneal treatment and high-density treatment. Then, the conformal layer 20 and the pad nitride layer 14 and the pad oxide layer 12 are released. Then, the oxide-filling material 22 is flattened so that it is flush with the surface of a substrate.

公开(公告)号：DE3787993T2

公开(公告)日：1994-05-19

申请号：DE3787993

申请日：1987-04-22

Applicant: IBM

Inventor： FLAITZ PHILIP LEE ,  FLANAGAN ARLYNE MARIE ,  HARVILCHUCK JOSEPH MATTHEW ,  HERRON LESTER WYNN ,  KNICKERBOCKER JOHN ULRICH ,  NUFER ROBERT WOLFF ,  PERRY CHARLES HAMPTON ,  REDDY SRINIVASA N

IPC: C04B35/638 ,  C04B35/64 ,  H01L21/48

公开(公告)号：DE3888225T2

公开(公告)日：1994-09-22

申请号：DE3888225

申请日：1988-03-25

Applicant: IBM

Inventor： FLAITZ PHILIP LEE ,  MASTER RAJ NAVINCHANDRA ,  PALMATEER PAUL HARRY ,  REDDY SRINIVASA S N

IPC: B23K20/00 ,  C04B37/02 ,  C04B41/51 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  H05K1/03 ,  H05K3/38 ,  B32B18/00 ,  B22F7/02 ,  B32B15/04

公开(公告)号：DE3888225D1

公开(公告)日：1994-04-14

申请号：DE3888225

申请日：1988-03-25

Applicant: IBM

Inventor： FLAITZ PHILIP LEE ,  MASTER RAJ NAVINCHANDRA ,  PALMATEER PAUL HARRY ,  REDDY SRINIVASA S N

IPC: B23K20/00 ,  C04B37/02 ,  C04B41/51 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  H05K1/03 ,  H05K3/38 ,  B32B18/00 ,  B22F7/02 ,  B32B15/04

公开(公告)号：DE3787993D1

公开(公告)日：1993-12-09

申请号：DE3787993

申请日：1987-04-22

Applicant: IBM

Inventor： FLAITZ PHILIP LEE ,  FLANAGAN ARLYNE MARIE ,  HARVILCHUCK JOSEPH MATTHEW ,  HERRON LESTER WYNN ,  KNICKERBOCKER JOHN ULRICH ,  NUFER ROBERT WOLFF ,  PERRY CHARLES HAMPTON ,  REDDY SRINIVASA N

IPC: C04B35/638 ,  C04B35/64 ,  H01L21/48

公开(公告)号：DE3673850D1

公开(公告)日：1990-10-11

申请号：DE3673850

申请日：1986-04-04

Applicant: IBM

Inventor： CHURCHWELL ROBERT WILLIAM ,  FLAITZ PHILIP LEE ,  HUMENIK JAMES NOEL

IPC: H01L23/50 ,  H01L21/48 ,  H01R12/04 ,  H05K3/34

Abstract: A method for use in brazing an interconnect pin to a portion of metallization pattern (e.g. a pad) existing on a brittle dielectric substrate, such as a multi-layered ceramic (MLC) substrate, is disclosed.