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    SEMICONDUCTOR WAFER TEST AND BURN-IN
    1.
    发明申请
    SEMICONDUCTOR WAFER TEST AND BURN-IN 审中-公开
    半导体波形测试和烧结

    公开(公告)号：WO9706444A1

    公开(公告)日：1997-02-20

    申请号：PCT/US9612544

    申请日：1996-08-09

    Applicant: IBM

    Inventor： LEAS JAMES MARC ,  KOSS ROBERT WILLIAM ,  VAN HORN JODY JOHN ,  WALKER GEORGE FREDERICK ,  PERRY CHARLES HAMPTON ,  GARDELL DAVID LEWIS ,  DINGLE STEVE LEO ,  PRILIK RONALD

    IPC: G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R31/316

    CPC classification number: G01R1/07385 ,  G01R1/07314 ,  G01R31/2863 ,  G01R31/2879 ,  G01R31/2886 ,  G01R31/2889

    Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the products chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

    Abstract translation: 用于在产品晶片上的所有集成电路芯片中同时测试或燃烧的装置和方法。 该装置包括具有测试芯片的玻璃陶瓷载体和用于连接到产品晶片上的大量芯片的焊盘的装置。 测试芯片上的稳压器提供了产品芯片上的电源和电源焊盘之间的接口，每个产品芯片至少有一个电压调节器。 电压调节器向产品芯片提供指定的Vdd电压，由此Vdd电压基本上与产品芯片所消耗的电流无关。 电压调节器或其他电子装置限制电流到任何产品芯片，如果它有一个短。 电压调节器电路可以是门控和可变的，并且其可以具有延伸到产品芯片的传感器线路。 测试芯片还可以提供测试功能，例如测试模式和用于存储测试结果的寄存器。

    4.
    发明专利
    未知

    公开(公告)号：DE69300907D1

    公开(公告)日：1996-01-11

    申请号：DE69300907

    申请日：1993-08-24

    Applicant: IBM

    Inventor： KNICKERBOCKER JOHN ULRICH ,  PERRY CHARLES HAMPTON ,  WALL DONALD RENE

    IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46

    Abstract: Disclosed is a multilayer ceramic substrate (30) for electronic applications including: (a) at least one internal layer (32) having vias (34) filled with a metallic material; (b) at least one sealing layer (40) having vias (42) filled with a composite material that is a mixture of ceramic and metallic materials; and (c) at least one transition layer (46) located between the internal and sealing layers having vias (48) filled with a composite material that is a mixture of ceramic and metallic materials but having less ceramic and more metallic material than the sealing layer vias and less metallic material than the internal layer vias. Also disclosed is a method of forming the multilayer ceramic substrate.

    8.
    发明专利
    未知

    公开(公告)号：DE69300907T2

    公开(公告)日：1996-06-20

    申请号：DE69300907

    申请日：1993-08-24

    Applicant: IBM

    Inventor： KNICKERBOCKER JOHN ULRICH ,  PERRY CHARLES HAMPTON ,  WALL DONALD RENE

    IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46

    Abstract: Disclosed is a multilayer ceramic substrate (30) for electronic applications including: (a) at least one internal layer (32) having vias (34) filled with a metallic material; (b) at least one sealing layer (40) having vias (42) filled with a composite material that is a mixture of ceramic and metallic materials; and (c) at least one transition layer (46) located between the internal and sealing layers having vias (48) filled with a composite material that is a mixture of ceramic and metallic materials but having less ceramic and more metallic material than the sealing layer vias and less metallic material than the internal layer vias. Also disclosed is a method of forming the multilayer ceramic substrate.

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