-
Patent Agency Ranking
公开(公告)号：JP2004158841A
公开(公告)日：2004-06-03
申请号：JP2003348861
申请日：2003-10-07
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： GAIDIS MICHAEL
IPC: H01L27/10 , G11C11/02 , H01L21/768 , H01L21/82 , H01L21/8246 , H01L27/105 , H01L27/22
CPC classification number: H01L21/76802 , H01L21/76838 , H01L27/222
Abstract: PROBLEM TO BE SOLVED: To embed a MRAM memory or a similar structure in a post-process of a logic or general-purpose integrated circuit, while maintaining the dimension required for the good performance of the MRAM and good operation of the logic circuit.
SOLUTION: By setting the standard vertical dimension of a BEOL at a value suitable for a logic circuit, an MRAM cell is arranged in the upper region (BEOL) of an integrated circuit. In the region where the MRAM cells should be arranged, the (N+1)th layer is separately etched. Standard etching is applied in a logic region, and deeper etching is applied in the MRAM region. Thereby, an interlayer interval in the logic region is a standard value, and the interlayer interval in the MRAM region can be a lower value that is suitable for allowing the vertical dimension of a material layer that goes into the MRAM cell.
COPYRIGHT: (C)2004,JPO-
-
公开(公告)号：AT503252T
公开(公告)日：2011-04-15
申请号：AT07867608
申请日：2007-12-04
Applicant: IBM
Inventor： GAIDIS MICHAEL , CLEVENGER LAWRENCE , DALTON TIMOTHY , DEBROSSE JOHN , HSU LOUIS , RADENS CARL , WONG KEITH , YANG CHIH-CHAO
Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
-
公开(公告)号：DE102004027663B4
公开(公告)日：2009-04-02
申请号：DE102004027663
申请日：2004-06-07
Applicant: IBM , QIMONDA AG
Inventor： ARNDT CHRISTIAN , COSTRINI GREG , GAIDIS MICHAEL , NING XIANG JAY , NUETZEL JOACHIM
IPC: H01L27/22 , G11C11/15 , H01L21/768 , H01L21/8246 , H01L43/12
Abstract: A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.
-
公开(公告)号：DE102004027663A1
公开(公告)日：2005-03-24
申请号：DE102004027663
申请日：2004-06-07
Applicant: IBM , INFINEON TECHNOLOGIES AG
Inventor： ARNDT CHRISTIAN , COSTRINI GREG , GAIDIS MICHAEL , NING XIANG JAY , NUETZEL JOACHIM
IPC: H01L21/768 , H01L21/8246 , H01L27/22 , H01L43/12 , G11C11/15
Abstract: A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.
-
-
-
-
Search Results
5
records
(took 0.02 seconds)
