公开(公告)号：WO02056340A3

公开(公告)日：2003-06-26

申请号：PCT/GB0105716

申请日：2001-12-21

Applicant: IBM ,  IBM UK

Inventor： CABRAL CYRIL ,  CLEVENGER LAWRENCE ,  HSU LOUIS LU-CHEN ,  WONG KEITH KWONG HON

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/525 ,  H01L27/06 ,  H01L23/64

CPC classification number: H01L21/76849 ,  H01L21/7687 ,  H01L21/76888 ,  H01L23/5258 ,  H01L27/0629 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes at least one fuse, resistor, diffusion barrier or capacitor that is formed of refractory metal-silicon-nitrogen. A suitable refractory material is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N.

Abstract translation: 半导体结构包括由难熔金属硅 - 氮形成的至少一个熔丝，电阻器，扩散阻挡层或电容器。 合适的耐火材料是TaSiN，其通过改变Ta:Si:N的比例来提供宽范围的电阻率。

公开(公告)号：WO0169664A3

公开(公告)日：2001-12-20

申请号：PCT/GB0101084

申请日：2001-03-13

Applicant: IBM ,  IBM UK

Inventor： NAEEM MUNIR ,  CLEVENGER LAWRENCE

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/285 ,  B81C1/00

CPC classification number: H01L21/76892 ,  H01L23/528 ,  Y10S977/715 ,  Y10S977/73 ,  Y10S977/762 ,  Y10S977/832

Abstract: A method is disclosed for forming microscale features with conventional multilayer structures. The method generally entails forming a multilayer structure (10) that includes a polycrystalline layer (12) and at least one constraining layer (14). The multilayer structure is patterned to form first (16) and second structures (18), each of which includes the polycrystalline and constraining layers. At least the first structure (16) is then locally heated, during which time the constraining layer restricts the thermal expansion of the polycrystalline layer of the first structure. As a result, stresses are induced in the polycrystalline layer of the first structure, causing substantially two-dimensional grain growth from the edge of the first structure. Sufficient grain growth occurs to produce a third structure (20) which, based on the grain size of the polycrystalline layer, will be a nano-scale structure. When appropriately configured, nano-scale structures can be formed as operative components of electrical, mechanical, optical and fluid-handling devices.

Abstract translation: 公开了一种用常规多层结构形成微尺度特征的方法。 该方法通常需要形成包括多晶层（12）和至少一个约束层（14）的多层结构（10）。 图案化多层结构以形成第一（16）和第二结构（18），其中每一个包括多晶和约束层。 至少第一结构（16）然后被局部加热，在此期间约束层限制第一结构的多晶层的热膨胀。 结果，在第一结构的多晶层中引起应力，从第一结构的边缘引起基本上二维的晶粒生长。 发生足够的晶粒生长以产生基于多晶层的晶粒尺寸将是纳米级结构的第三结构（20）。 当适当配置时，纳米级结构可以形成为电气，机械，光学和流体处理装置的有效部件。

公开(公告)号：WO0231867A3

公开(公告)日：2002-10-17

申请号：PCT/GB0104430

申请日：2001-10-05

Applicant: IBM ,  IBM UK

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ,  HSU LOUIS LU-CHEN ,  WONG KWONG HON

IPC: H01L21/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0688

Abstract: Electronic structure that has in-situ formed resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The structure may be combined with a capacitor network to form RC circuits.

Abstract translation: 具有原位形成的电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件，形成在顶部上并与第一多个导电元件中的至少一个电连通的多个电阻通孔，以及 形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。 该结构还可以形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。 该结构可以与电容器网络组合以形成RC电路。

公开(公告)号：JP2007306008A

公开(公告)日：2007-11-22

申请号：JP2007141486

申请日：2007-05-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CYRILLE CABRAL JR ,  CLEVENGER LAWRENCE ,  HSU LOUIS ,  WONG KEITH KWONG HON

IPC: H01L21/8242 ,  C23C14/00 ,  C23C14/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/318 ,  H01L27/108

CPC classification number: H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

Abstract: PROBLEM TO BE SOLVED: To provide the method of forming a capacitor on an original position in a semiconductor structure.
SOLUTION: First, a previously-treated semiconductor substrate is positioned in a sputtering chamber. Then, Ar gas is flown into the sputtering chamber and a first heat-resistant metal-silicon-nitrogen layer is adhered in a sputtering manner onto the substrate from the target of heat-resistant metal silicide or two targets of heat-resistant metal and silicon. Then, N
2 gas is flown into the sputtering chamber until the density of N
2 gas in the chamber reaches at least 35%, and a second heat-resistant metal-silicon-nitrogen layer is adhered in the sputtering manner onto the first heat-resistant metal-silicon-nitrogen layer. Then, the flow of N
2 gas is stopped and a third heat-resistant metal-silicon-nitrogen layer is adhered in the sputtering manner onto the second heat-resistant metal-silicon-nitrogen layer. Then, the multilayer stack of heat-resistant metal-silicon-nitrogen is formed on the capacitor using photolithography.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供在半导体结构中的原始位置形成电容器的方法。 解决方案：首先，将预先处理的半导体衬底放置在溅射室中。 然后，将Ar气体流入溅射室，并且将第一耐热金属硅 - 氮层从耐热金属硅化物的靶或两个耐热金属和硅的靶以溅射方式附着到基板上 。 然后，将N 2 气体流入溅射室，直到室内的N 2 SB 2气体的密度达到至少35％，而第二耐热金属硅 - 氮层以溅射方式粘附到第一耐热金属 - 硅 - 氮层上。 然后，停止N SB 2气体的流动，并且以溅射方式将第三耐热金属 - 硅 - 氮层粘附到第二耐热金属 - 硅 - 氮层上。 然后，使用光刻法在电容器上形成多层叠层的耐热金属硅 - 氮。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003060084A

公开(公告)日：2003-02-28

申请号：JP2002149960

申请日：2002-05-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CYRILLE CABRAL JR ,  CLEVENGER LAWRENCE ,  HSU LOUIS ,  WONG KEITH KWONG HON

IPC: C23C14/00 ,  C23C14/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a capacitor at a source position inside a semiconductor structure.
SOLUTION: In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to deposit by sputtering a first refractory metal-silicon-nitrogen layer 14 on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N
2 gas is then flown into the sputtering chamber until that the concentration of N
2 gas in the camber is at least 35% to deposit by sputtering a second refractory metal-silicon-nitrogen layer 16 on top of the first refractory metal-silicon-nitrogen layer. The N
2 gas flow is then stopped to deposit by sputtering a third refractory metal-silicon-nitrogen layer 18 on top of the second refractory metal-silicon-nitrogen layer. The multi- layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into the capacitor.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种在半导体结构内的源极位置形成电容器的方法。 解决方案：在该方法中，首先将预处理的半导体衬底放置在溅射室中。 然后通过从难熔金属硅化物靶或从难熔金属和硅的两个靶溅射基底上的第一难熔金属硅 - 氮层14，将Ar气体流入溅射室中。 然后将N 2气体流入溅射室，直到通过在第一耐火金属 - 硅 - 氮层的顶部溅射第二难熔金属 - 硅 - 氮层16来沉积外弧中的N 2气体的浓度至少为35％ 。 然后通过在第二难熔金属 - 硅 - 氮层的顶部溅射第三耐火金属 - 硅 - 氮层18来停止N2气流以沉积。 然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

公开(公告)号：WO0137325A9

公开(公告)日：2002-07-04

申请号：PCT/US0031227

申请日：2000-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE ,  COSTRINI GREG ,  DOBUZINSKY DAVE ,  OTANI YOICHI ,  RUPP THOMAS ,  SARDESAI VIRAJ

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/76802

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000watts under a pressure of 50 - 400mTorr. The gas mixture includes 2 - 30sccm of C4F8, 20 - 80sccm of CO, 2 - 30sccm of O2 and 50 - 400sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

Abstract translation: 在集成电路芯片中形成导线的镶嵌方法。 通过在压力为50-400mTorr的500-3000瓦电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2 - 30sccm的C4F8，20 - 80sccm的CO，2 - 30sccm的O2和50 - 400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。

公开(公告)号：WO0137325A2

公开(公告)日：2001-05-25

申请号：PCT/US0031227

申请日：2000-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE ,  COSTRINI GREG ,  DOBUZINSKY DAVE ,  OTANI YOICHI ,  RUPP THOMAS ,  SARDESAI VIRAJ

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/31116 ,  H01L21/76802

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000watts under a pressure of 50 - 400mTorr. The gas mixture includes 2 - 30sccm of C4F8 2

Abstract translation: 在集成电路芯片中形成导线的镶嵌方法。 通过在压力为50-400mTorr的500-3000瓦电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2-30sccm的C 4 F 8，20-80sccm的CO，2-30sccm的O> 2和50-400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。

公开(公告)号：DE60137492D1

公开(公告)日：2009-03-12

申请号：DE60137492

申请日：2001-03-13

Applicant: IBM ,  IBM UK

Inventor： NAEEM MUNIR ,  CLEVENGER LAWRENCE

IPC: H01L21/28 ,  H01L21/285 ,  B81C1/00 ,  H01L21/768

Abstract: A method of forming nano-scale features with conventional multilayer structures, and nano-scale features formed thereby. The method generally entails forming a multilayer structure that includes a polycrystalline layer and at least one constraining layer. The multilayer structure is patterned to form first and second structures, each of which includes the polycrystalline and constraining layers. At least the first structure is then locally heated, during which time the constraining layer restricts the thermal expansion of the polycrystalline layer of the first structure. As a result, stresses are induced in the polycrystalline layer of the first structure, causing substantially two-dimensional grain growth from the edge of the first structure. Sufficient grain growth occurs to produce a third structure which, based on the grain size of the polycrystalline layer, will be a nano-scale structure. When appropriately configured, nano-scale structures can be formed as operative components of electrical, mechanical, optical and fluid-handling devices.

公开(公告)号：DE112019003048T5

公开(公告)日：2021-03-04

申请号：DE112019003048

申请日：2019-07-18

Applicant: IBM

Inventor： RUBIN JOSHUA ,  CLEVENGER LAWRENCE ,  ARVIN CHARLES LEON

IPC: H01L23/538 ,  H01L25/065

Abstract: Es werden Multi-Chip-Packungsstrukturen und Verfahren für ein Aufbauen von Multi-Chip-Packungsstrukturen bereitgestellt, die Chip-Zwischenverbindungs-Brückeneinheiten einsetzen, die so ausgelegt sind, dass eine hohe Zwischenverbindungsdichte zwischen benachbarten Chips (oder Einzelchips) in der Packungsstruktur bereitgestellt werden, ebenso wie vertikale Leistungsverteilungsleiterbahnen durch die Chip-Zwischenverbindungs-Brückeneinheit bereitgestellt werden, um Leistungs(und Masse)-Verbindungen von einem Packungssubstrat zu den Chips bereitzustellen, die mit der Chip-Zwischenverbindungs-Brückeneinheit verbunden sind.

公开(公告)号：AT503252T

公开(公告)日：2011-04-15

申请号：AT07867608

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL ,  CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  DEBROSSE JOHN ,  HSU LOUIS ,  RADENS CARL ,  WONG KEITH ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.