MANUFACTURE METHOD FOR NOBLE METAL OXIDE AND STRUCTURE FORMED FROM THE NOBLE METAL OXIDE

    公开(公告)号:JPH11224936A

    公开(公告)日:1999-08-17

    申请号:JP29838198

    申请日:1998-10-20

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a method for improving adhesion and interfacial characteristics between a noble metal part and a high-permeability film by exposing a surface of a noble-metal substrate to oxygen-containing energy and forming a noble-metal oxide film. SOLUTION: One of or a combination of high-density microwave, high-frequency plasma, ion collisions due to oxygen-containing ion beam is selected as an oxygen-containing energy source, and the energy source is used with or without a substrate bias under separate control. The noble metal is selected from among at least on of Pt, Ir, Au, Os, Ag, Pd, Rh and Ru, or selected from among a noble metal alloy of these noble metals. A noble metal oxide film 36 is formed on a noble-metal substrate 34, by exposing a surface of the substrate 34 to the oxygen containing energy source. The oxide layer thickness is normally in a range of 0.4 to 10 nm. In addition, the surface of the noble- metal substrate 34 may be exposed to the oxygen containing energy source for a sufficient time to form an interfacial reinforcement layer, and then a high-permeability material layer 38 may be deposited on the noble-metal substrate 34 with the oxygen containing layer in between.

    SPACER INTEGRATION SCHEME IN MRAM TECHNOLOGY
    3.
    发明申请
    SPACER INTEGRATION SCHEME IN MRAM TECHNOLOGY 审中-公开
    MRAM技术中的间隔整合方案

    公开(公告)号:WO2004032144A3

    公开(公告)日:2004-08-05

    申请号:PCT/EP0310678

    申请日:2003-09-24

    CPC classification number: H01L43/12

    Abstract: A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

    Abstract translation: 通过蚀刻由缓冲层,钉扎磁性层,隧道势垒层和自由磁性层组成的覆盖金属堆叠来制造磁阻存储器件。 通过形成覆盖自由层和隧道屏障界面侧面的保护性间隔物,消除了在蚀刻过程期间与溅射金属接合短路的问题。 在通过在阻挡层上停止的自由层的第一次蚀刻之后形成间隔物。 在间隔物形成之后,进行第二次蚀刻以隔离该装置。 器件隧道结的图案化使用一次性心轴方法制造,其能够在器件图案化工艺完成之后进行自对准接触。

    PATTERNING METAL STACK LAYERS OF MAGNETIC SWITCHING DEVICE, UTILIZING A BILAYER METAL HARDMASK
    4.
    发明申请
    PATTERNING METAL STACK LAYERS OF MAGNETIC SWITCHING DEVICE, UTILIZING A BILAYER METAL HARDMASK 审中-公开
    磁性切换装置的金属堆叠层,利用双层金属硬质合金

    公开(公告)号:WO2004040602A2

    公开(公告)日:2004-05-13

    申请号:PCT/EP0312017

    申请日:2003-10-29

    CPC classification number: G11C11/16 B82Y25/00 B82Y40/00 H01F41/308 H01L43/12

    Abstract: The invention relates to magnetic switching devices, and more particularly to a method for patterning metal stack layers of a magnetic switching device utilizing TiN and W as a bilayer metal hardmask (7, 8) patterned in two lithography steps with concommitant hardmask open etch and resist strip steps. The hardmask materials TiN and W are chosen so that the mask open etch chemistry is designed with good selectivity, thereby enabling patterning of the hardmask layers prior to etching of the metal stack layers.

    Abstract translation: 本发明涉及磁性开关器件,更具体地说,涉及一种利用TiN和W作为双层金属硬掩模(7,8)图案化的磁性开关器件的金属堆叠层的方法,该双层金属硬掩模(7,8)在两个光刻步骤中图案化,并具有硬掩模开放蚀刻和抗蚀剂 剥离步骤。 选择硬掩模材料TiN和W,使得掩模开口蚀刻化学品被设计成具有良好的选择性,从而能够在刻蚀金属叠层之前对硬掩模层进行图案化。

    5.
    发明专利
    未知

    公开(公告)号:DE102005034667A1

    公开(公告)日:2006-03-23

    申请号:DE102005034667

    申请日:2005-07-25

    Abstract: The invention relates to a method of encapsulating conductive lines of semiconductor devices and a structure thereof. An encapsulating protective material, such as TaN, Ta, Ti, TiN, or combinations thereof is disposed over conductive lines of a semiconductor device. The encapsulating protective material protects the conductive lines from harsh etch chemistries when a subsequently deposited material layer is patterned and etched. The encapsulating protective material is conductive and may be left remaining in the completed semiconductor device. The encapsulating material is patterned using a masking material, and processing of the semiconductor device is then continued. The masking material may be left remaining in the structure as part of a subsequently deposited insulating material layer.

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