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    SPACER INTEGRATION SCHEME IN MRAM TECHNOLOGY
    1.
    发明申请
    SPACER INTEGRATION SCHEME IN MRAM TECHNOLOGY 审中-公开
    MRAM技术中的间隔整合方案

    公开(公告)号：WO2004032144A3

    公开(公告)日：2004-08-05

    申请号：PCT/EP0310678

    申请日：2003-09-24

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： COSTRINI GREG ,  HUMMEL JOHN P ,  LOW KIA-SENG ,  FINDEIS FRANK ,  KASKO IGOR ,  RABERG WOLFGANG

    IPC: G11B5/127 ,  G11B5/33 ,  G11C11/00 ,  G11C11/15 ,  G11C11/34 ,  H01L21/00 ,  H01L21/331 ,  H01L21/335 ,  H01L21/8232 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22 ,  H01L31/0352 ,  H01L43/12

    CPC classification number: H01L43/12

    Abstract: A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

    Abstract translation: 通过蚀刻由缓冲层，钉扎磁性层，隧道势垒层和自由磁性层组成的覆盖金属堆叠来制造磁阻存储器件。 通过形成覆盖自由层和隧道屏障界面侧面的保护性间隔物，消除了在蚀刻过程期间与溅射金属接合短路的问题。 在通过在阻挡层上停止的自由层的第一次蚀刻之后形成间隔物。 在间隔物形成之后，进行第二次蚀刻以隔离该装置。 器件隧道结的图案化使用一次性心轴方法制造，其能够在器件图案化工艺完成之后进行自对准接触。

    METHOD OF MANUFACTURING FERROELECTRIC-MATERIAL CAPACITOR
    2.
    发明专利
    METHOD OF MANUFACTURING FERROELECTRIC-MATERIAL CAPACITOR 失效

    公开(公告)号：JP2001244425A

    公开(公告)日：2001-09-07

    申请号：JP2001051142

    申请日：2001-02-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER DR ,  WEINRICH VOLKER ,  KASKO IGOR

    IPC: H01L27/105 ,  H01L21/02 ,  H01L21/8246

    Abstract: PROBLEM TO BE SOLVED: To provide an executable method of manufacturing, with only a little labor, a ferroelectric-material capacitor having two pieces or more of withstand voltage which are different from each other. SOLUTION: First, a first electrode structure 11 having the surface which forms at least two-height levels is formed on a substrate 1, a ferroelectric- material layer 13 having a variety of layer thickness is laminated on the first electrode structure 11 by spin coating, and in succession, a second electrode structure 12 is formed on the ferroelectric-material layer 13.

    METHOD FOR PRODUCING FERROELECTRIC MEMORY CELLS
    4.
    发明申请
    METHOD FOR PRODUCING FERROELECTRIC MEMORY CELLS 审中-公开
    用于生产FERRO电记忆CELL

    公开(公告)号：WO02078084A2

    公开(公告)日：2002-10-03

    申请号：PCT/DE0201054

    申请日：2002-03-22

    Applicant: INFINEON TECHNOLOGIES AG ,  KASKO IGOR ,  KROENKE MATTHIAS

    Inventor： KASKO IGOR ,  KROENKE MATTHIAS

    IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246

    CPC classification number: H01L21/76855 ,  H01L21/7687 ,  H01L21/76888 ,  H01L28/55 ,  H01L28/75

    Abstract: The invention relates to a method for producing ferroelectric memory cells in accordance with the stack principle. According to said method, an adhesive layer (2, 3) is formed between a lower capacitor electrode (6) of a memory capacitor and a conductive plug (1), which is formed below said electrode and makes an electric connection between said capacitor electrode (6) and a transistor electrode of a selection transistor that is formed in or on a semiconductor wafer. An oxygen diffusion barrier (4, 5) is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. The method is characterised by the following steps: (A) Determination of the oxygen speed of the adhesive layer (2, 3) and the diffusion coefficient (DOxygen(T)) of oxygen in the material of the adhesive layer (2, 3), dependent on the temperature (T); (B) Determination of the diffusion coefficient (DSilicon(T)) of silicon in the material of the adhesive layer (2, 3), dependent on the temperature and (C) Calculation of an optimal temperature range for the RTP step from the two diffusion coefficients, (DOxygen(T)) and (DSilicon(T)) that have been determined for a predetermined layer thickness (dBARR) and layer width (bBARR) of the layer system consisting of the adhesive layer and the oxygen diffusion barrier, so that during the RTP step the siliconisation of the adhesive layer occurs more rapidly than its oxidation.

    Abstract translation: 本发明涉及一种用于铁电存储器单元的制备根据堆栈原则，其中，下电容器电极（6）之间的存储电容器和底层形成的导电插塞（1），用于电连接所述（6），其具有一个的晶体管电极电容器电极中或上 走秀半导体晶片选择晶体管形成，粘接层（2，3）和粘合剂层的氧扩散阻挡层（4,5）形成，并进行强电介质的沉积之后的RTP步骤在氧气气氛中，所述方法的特征在于以下步骤：（ A）测定，所述粘合剂层的氧化速率（2，3）和扩散系数（DSauerstoff（T）在粘合剂层（2的材料中的氧的），3）中的温度（T）的依赖性; （B）在所述粘合剂层的材料中的硅的扩散系数（DSilizium（T））的计算（2,3）（取决于温度和（C）计算最优的温度范围内，用于从先前确定的两个扩散系数的RTP步骤DSauerstoff （T）和DSilizium（T））（对于给定的层厚度dBARR）和氧扩散阻挡，使得在RTP步骤中，粘合剂层的硅化比其氧化得更快。

    METHOD FOR PRODUCING FERROELECTRIC CAPACITORS AND INTEGRATED SEMICONDUCTOR MEMORY CHIPS
    6.
    发明申请
    METHOD FOR PRODUCING FERROELECTRIC CAPACITORS AND INTEGRATED SEMICONDUCTOR MEMORY CHIPS 审中-公开
    用于生产FERRO电气电容和集成半导体内存块

    公开(公告)号：WO02065518A3

    公开(公告)日：2002-11-21

    申请号：PCT/DE0104790

    申请日：2001-12-18

    Applicant: INFINEON TECHNOLOGIES AG ,  KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

    Inventor： KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

    IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115

    CPC classification number: H01L21/7687 ,  H01L21/76888 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    Abstract: The invention relates to a method for the production of ferroelectric capacitors structured according to the stack principle, which are used in integrated semiconductor memory chips, wherein the individual capacitor modules (10, 11) have an oxygen barrier (4a, 4b) between a lower capacitor electrode (5a, 5b) and an electrically conductive plug (1a, 1b). At a site where it is not covered by the corresponding oxygen barrier (4a, 4b), an unstructured adhesive layer (3) is oxidized by the oxygen arising during the tempering process of the ferroelectric (6a, 6b) and forms insulating segments at said site in such a way that the lower capacitor electrodes (5a, 5b) of the ferroelectric capacitors (10, 11) are electrically insulated from one another. This makes it possible to eliminate the structuring step of the adhesive layer (3). Furthermore, said layer (3) serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.

    Abstract translation: 在用于生产在堆栈原则强电介质电容器建成为在集成的半导体存储器装置中使用的方法，所述个别电容器模块（10，11）具有氧阻隔（4A，4B）的下电容器电极之间（5A，5B）和导电插头（1A， 图1b）。 非结构化Hafschicht（3），在那里它们（4A，4B）是通过在铁电体的退火过程中的氧所覆盖的相应的氧屏障的不（6A，6B）形成，氧化的和形式的绝缘部分，使得下 电容器电极（图5a中，铁电电容器（10的​​5B9，11）彼此电绝缘。这消除了对粘接剂层（3），并且还，该层（3）可以被用于堵塞用于吸杂氧和抑制氧气扩散的图案化步骤。

    8.
    发明专利
    未知

    公开(公告)号：DE10112276C2

    公开(公告)日：2003-02-06

    申请号：DE10112276

    申请日：2001-03-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KROENKE MATTHIAS ,  KASKO IGOR ,  WEINRICH VOLKER

    IPC: H01L21/02 ,  H01L21/285 ,  H01L27/115 ,  H01L27/11502 ,  H01L21/8239 ,  H01L27/105

    Abstract: The integrated ferroelectric semiconductor memory is fabricated according to the stack cell principle. A ferroelectric capacitor module is formed on an intermediate oxide above a selection transistor located in or on a semiconductor wafer. The capacitor module is brought into conductive contact by its bottom capacitor electrode with an electrode of the selection transistor by means of an electrically conductive plug leading through the intermediate oxide. A layer system of a conductive oxygen diffusion barrier and a conductive adhesion layer is deposited directly below the bottom capacitor electrode, and the adhesion layer and the overlying oxygen diffusion barrier are deposited directly into the contact hole and form the plug at least in the region lying directly below the bottom capacitor electrode.

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