公开(公告)号：EP0794567A3

公开(公告)日：2000-01-12

申请号：EP97102901

申请日：1997-02-21

Applicant: SIEMENS AG ,  IBM

Inventor： HO HERBERT L ,  SRINIVASAN RADHIKA ,  HALLE SCOTT D ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  MANDELMAN JACK A ,  JASO MARK ANTHONY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10861 ,  H01L21/76232 ,  H01L27/10832 ,  H01L28/82 ,  Y10S438/973

Abstract: A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.

公开(公告)号：DE69618543T2

公开(公告)日：2002-09-12

申请号：DE69618543

申请日：1996-10-21

Applicant: IBM

Inventor： JASO MARK ANTHONY

IPC: H01L21/768 ,  C23F1/14 ,  H01L21/304 ,  H01L21/3105

Abstract: A method of forming metal patterns in an insulating layer on a semiconductor wafer. After Chem-Mech Polishing (CMP) the insulating layer and forming studs in a planarized insulating layer, the polished surface is chem-mech polished with a touch-up slurry. The touch-up slurry has a nearly identical removal rate for the stud material (tungsten or titanium) as for the insulating material (SiO2). The preferred non-selective slurry is fumed colloidal silica, 8% by weight, and 20 g/l ammonium persulfate.

公开(公告)号：DE69618543D1

公开(公告)日：2002-02-21

申请号：DE69618543

申请日：1996-10-21

Applicant: IBM

Inventor： JASO MARK ANTHONY

IPC: H01L21/768 ,  C23F1/14 ,  H01L21/304 ,  H01L21/3105

Abstract: A method of forming metal patterns in an insulating layer on a semiconductor wafer. After Chem-Mech Polishing (CMP) the insulating layer and forming studs in a planarized insulating layer, the polished surface is chem-mech polished with a touch-up slurry. The touch-up slurry has a nearly identical removal rate for the stud material (tungsten or titanium) as for the insulating material (SiO2). The preferred non-selective slurry is fumed colloidal silica, 8% by weight, and 20 g/l ammonium persulfate.

公开(公告)号：DE69618548D1

公开(公告)日：2002-02-21

申请号：DE69618548

申请日：1996-10-24

Applicant: IBM

Inventor： ARMACOST MICHAEL DAVID ,  DOBUZINSKY DAVID MARK ,  GAMBINO JEFFERY PETER ,  JASO MARK ANTHONY

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/321 ,  H01L21/3105

Abstract: A method of forming interlevel studs in an insulating layer on a semiconductor wafer. First, a conformal BPSG layer is formed on a Front End of the Line (FEOL) semiconductor structure. Vias are opened through the BPSG layer to the FEOL structure. A layer of poly is formed (deposited) on the BPSG layer, filling the vias. The poly layer may be insitu doped poly or implanted after it is deposited. The wafer is annealed to diffuse dopant from the poly to form diffusions wherever the poly contacts the substrate. A non-selective slurry of colloidal silica and at least 1% ammonium hydroxide is used to chem-mech polish the poly from the BPSG layer and, simultaneously, planarize the BPSG layer.

公开(公告)号：DE69214087T2

公开(公告)日：1997-04-03

申请号：DE69214087

申请日：1992-10-09

Applicant: IBM

Inventor： JASO MARK ANTHONY ,  JONES PAUL BRADLEY ,  MEYERSON BERNARD STEELE ,  PATEL VISHNUBHAI VITTHALBHAI

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/311

公开(公告)号：DE69636808T2

公开(公告)日：2007-11-08

申请号：DE69636808

申请日：1996-11-08

Applicant: IBM

Inventor： GAMBINO JEFFREY PETER ,  JASO MARK ANTHONY ,  NESBIT LARRY ALAN

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/304 ,  H01L21/321

Abstract: Forming inter level studs of at least two different materials, in an insulating layer on a semiconductor wafer comprises: (a) forming a layer of insulating material on a semiconductor wafer; (b) planarising the insulating layer; (c) forming a first group of vias through the insulating layer; (d) forming a layer of first conducting material on the insulating layer; (e) forming a second group of vias through the first conducting material layer and insulating layer; (f) forming a layer of a second conductive material filling the first and second group of vias; (g) removing the second conductive layer to expose the first conductive material layer, such that the second conductive material remains only in the first and second via groups; and (h) removing the exposed first conductive material layer. Also claimed is the method as above in which steps (b),(h) and (i) are achieved by chemically-mechanically polishing, (c) and (e) are etched, and dopant is implanted into the wafer through the second group of vias and the wafer is annealed after (e).

公开(公告)号：DE69636808D1

公开(公告)日：2007-02-15

申请号：DE69636808

申请日：1996-11-08

Applicant: IBM

Inventor： GAMBINO JEFFREY PETER ,  JASO MARK ANTHONY ,  NESBIT LARRY ALAN

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/304 ,  H01L21/321

Abstract: Forming inter level studs of at least two different materials, in an insulating layer on a semiconductor wafer comprises: (a) forming a layer of insulating material on a semiconductor wafer; (b) planarising the insulating layer; (c) forming a first group of vias through the insulating layer; (d) forming a layer of first conducting material on the insulating layer; (e) forming a second group of vias through the first conducting material layer and insulating layer; (f) forming a layer of a second conductive material filling the first and second group of vias; (g) removing the second conductive layer to expose the first conductive material layer, such that the second conductive material remains only in the first and second via groups; and (h) removing the exposed first conductive material layer. Also claimed is the method as above in which steps (b),(h) and (i) are achieved by chemically-mechanically polishing, (c) and (e) are etched, and dopant is implanted into the wafer through the second group of vias and the wafer is annealed after (e).

公开(公告)号：DE69618548T2

公开(公告)日：2002-09-12

申请号：DE69618548

申请日：1996-10-24

Applicant: IBM

Inventor： ARMACOST MICHAEL DAVID ,  DOBUZINSKY DAVID MARK ,  GAMBINO JEFFERY PETER ,  JASO MARK ANTHONY

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/321 ,  H01L21/3105

Abstract: A method of forming interlevel studs in an insulating layer on a semiconductor wafer. First, a conformal BPSG layer is formed on a Front End of the Line (FEOL) semiconductor structure. Vias are opened through the BPSG layer to the FEOL structure. A layer of poly is formed (deposited) on the BPSG layer, filling the vias. The poly layer may be insitu doped poly or implanted after it is deposited. The wafer is annealed to diffuse dopant from the poly to form diffusions wherever the poly contacts the substrate. A non-selective slurry of colloidal silica and at least 1% ammonium hydroxide is used to chem-mech polish the poly from the BPSG layer and, simultaneously, planarize the BPSG layer.

公开(公告)号：DE69214087D1

公开(公告)日：1996-10-31

申请号：DE69214087

申请日：1992-10-09

Applicant: IBM

Inventor： JASO MARK ANTHONY ,  JONES PAUL BRADLEY ,  MEYERSON BERNARD STEELE ,  PATEL VISHNUBHAI VITTHALBHAI

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/311