公开(公告)号：GB2608308B

公开(公告)日：2025-04-16

申请号：GB202213056

申请日：2021-01-26

Applicant: IBM

Inventor： TIAN SHEN ,  HENG WU ,  KEVIN WAYNE BREW ,  JINGYUN ZHANG

IPC: H10N70/20 ,  G06N3/063 ,  G11C11/56 ,  G11C13/00 ,  H10N70/00

Abstract: A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode over a substrate, constructing a PCM stack including a plurality of PCM layers each having a different crystallization temperature over the bottom electrode, and forming a top electrode over the PCM stack. The crystallization temperature varies in an ascending order from the bottom electrode to the top electrode.

公开(公告)号：IL295321A

公开(公告)日：2022-10-01

申请号：IL29532122

申请日：2022-08-02

Applicant: IBM ,  TIAN SHEN ,  RUILONG XIE ,  KEVIN W BREW ,  HENG WU ,  JINGYUN ZHANG

Inventor： TIAN SHEN ,  RUILONG XIE ,  KEVIN W BREW ,  HENG WU ,  JINGYUN ZHANG

IPC: H01L45/00

Abstract: A phase change material switch includes a phase change layer disposed on a metal liner. A gate dielectric layer is disposed on the phase change layer. A metal gate liner is disposed on the gate dielectric layer.

公开(公告)号：GB2594428B

公开(公告)日：2022-03-16

申请号：GB202112164

申请日：2020-01-28

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  TAKASHI ANDO ,  ALEXANDER REZNICEK ,  JINGYUN ZHANG ,  POUYA HASHEMI

IPC: H01L45/00 ,  G11C13/00 ,  H01L21/335 ,  H01L27/24 ,  H01L29/66 ,  H01L29/78

Abstract: A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.

公开(公告)号：GB2609779B

公开(公告)日：2025-04-16

申请号：GB202215194

申请日：2021-02-19

Applicant: IBM

Inventor： TIAN SHEN ,  RUILONG XIE ,  KEVIN BREW ,  HENG WU ,  JINGYUN ZHANG

IPC: H10B63/10 ,  H10N70/00 ,  H10N70/20

Abstract: A phase change material switch includes a phase change layer disposed on a metal liner. A gate dielectric layer is disposed on the phase change layer. A metal gate liner is disposed on the gate dielectric layer.

公开(公告)号：GB2608308A

公开(公告)日：2022-12-28

申请号：GB202213056

申请日：2021-01-26

Applicant: IBM

Inventor： TIAN SHEN ,  HENG WU ,  KEVIN WAYNE BREW ,  JINGYUN ZHANG

IPC: H01L45/00 ,  G06N3/063 ,  G11C11/56 ,  G11C13/00

Abstract: A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode (12) over a substrate (10), constructing a PCM stack (20) including a plurality of PCM layers each having a different crystallization temperature over the bottom electrode (12), and forming a top electrode (32) over the PCM stack (20). The crystallization temperature varies in an ascending order from the bottom electrode (12) to the top electrode (32).

公开(公告)号：GB2603608A

公开(公告)日：2022-08-10

申请号：GB202117331

申请日：2021-12-01

Applicant: IBM

Inventor： JINGYUN ZHANG ,  TAKASHI ANDO ,  CHOONGHYUN LEE ,  ALEXANDER REZNICEK

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8238 ,  H01L29/423

Abstract: A method including forming nanosheet stacks 20 on a substrate 10, each nanosheet stack 20 including alternating layers of sacrificial semiconductor material and semiconductor channel material 18, removing sacrificial semiconductor material layers of the nanosheet stacks 20, forming a gate dielectric 24 surrounding the semiconductor channel layers 18 of the nanosheet stacks 20, and crystalizing the gate dielectric of a subset of the nanosheet stacks 20. The crystalized gate dielectric 32 may be formed by an annealing process. A dipole layer 34 may be formed over the gate dielectric 24 such that it surrounds the semiconductor channel layers 18, and the dipole material 34 may be diffused into the non-crystalized gate dielectric 24 of a second subset of stacks by a process of annealing. The different processes applied to the subsets of stacks may fabricate nanosheet transistors with different threshold voltages. The sacrificial semiconductor material may be silicon germanium, and the nanosheet stacks may form a FET or CMOS.

公开(公告)号：GB2594428A

公开(公告)日：2021-10-27

申请号：GB202112164

申请日：2020-01-28

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  TAKASHI ANDO ,  ALEXANDER REZNICEK ,  JINGYUN ZHANG ,  POUYA HASHEMI

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  H01L29/66 ,  H01L29/78

Abstract: A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.