公开(公告)号：EP1854131A4

公开(公告)日：2011-03-30

申请号：EP06849665

申请日：2006-01-12

Applicant: IBM

Inventor： DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

IPC: H01L21/20 ,  B05C11/00 ,  B32B3/26

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

公开(公告)号：JP2005311366A

公开(公告)日：2005-11-04

申请号：JP2005119003

申请日：2005-04-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  CHIRAS STEFANIE R ,  DALTON TIMOTHY ,  DEMAREST JAMES J ,  DUNN DERREN N ,  DZIOBKOWSKI CHESTER T ,  FLAITZ PHILIP L ,  LANE MICHAEL W ,  LLOYD JAMES R ,  DARYL D RESUTAINO ,  SHAW THOMAS M ,  WANG YUN YU ,  YANG CHIH-CHAO

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To realize an interconnection structure that improves the adhesion between an upper low-k dielectric layer and a diffusion barrier cap dielectric layer existing therebeneath. SOLUTION: In the interconnection structure, adhesion between the upper low-k (for example, the dielectric coefficient is less than 4.0) dielectric layer (for example, a dielectric containing an element group consisting of Si, C, O, and H) and the diffusion barrier cap dielectric layer (for example, a cap layer containing an element group consisting of C, Si, N, and H) existing therebeneath is improved, by providing an adhesion transition layer in between the two layers. Because the adhesion transition layer exists between the upper low-k dielectric layer and the diffusion barrier cap dielectric layer, the possibility that the layers in the interconnection structure are separated in a packaging process is reduced. The adhesion transition layer provided here comprises a lower SiO x (or SiON) contained region and an upper C inclination region. Such a structure and, in particular, a method for forming an adhesion transition layer are also provided. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：实现改善上部低k电介质层和存在于其之间的扩散阻挡盖电介质层之间的粘附性的互连结构。 解决方案：在互连结构中，上部低k（例如，介电系数小于4.0）电介质层（例如，包含由Si，C，O和 H）和扩散阻挡盖电介质层（例如，包含由C，Si，N和H构成的元素组的覆盖层）提高，通过在两层之间提供粘合过渡层。 由于粘附过渡层存在于上部低k电介质层和扩散阻挡层电介质层之间，因此在封装过程中互连结构中的层分离的可能性降低。 这里提供的粘合过渡层包含较低的SiO xS（或SiON）含有区域和上C倾斜区域。 还提供了这种结构，特别是形成粘附过渡层的方法。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2007089223A3

公开(公告)日：2007-11-01

申请号：PCT/US2006001154

申请日：2006-01-12

Applicant: IBM ,  DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

Inventor： DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

IPC: H01L21/20 ,  B05C11/00 ,  B32B3/26

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Abstract translation: 描述了一种用于形成具有受控双轴应力的超低介电常数层的方法，其包括通过PECVD和旋涂涂覆之一形成含有Si，C，O和H的层并且在包含非常低浓度 的氧气和水每个小于10ppm。 还通过使用介电常数不超过2.8的方法来描述材料。 本发明克服了形成低双轴应力小于46MPa的薄膜的问题。

公开(公告)号：SG145626A1

公开(公告)日：2008-09-29

申请号：SG2008010068

申请日：2008-02-05

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： RESTAINO DARRYL D ,  WIDODO JOHNNY ,  BONILLA GRISELDA ,  DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  KIM JAE H ,  LANE MICHAEL W ,  LIU XIAO H ,  NGUYEN SON V ,  SHAW THOMAS M

Abstract: BEOL INTERCONNECT STRUCTURES WITH IMPROVED RESISTANCE TO STRESS A chip is provided which includes a back-end-of-line ("BEOL") interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric ("ILD") layers which include a dielectric material curable by ultraviolet ("UV") radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

公开(公告)号：AU2002356887A1

公开(公告)日：2004-06-07

申请号：AU2002356887

申请日：2002-10-31

Applicant: IBM

Inventor： LANE MICHAEL W ,  LINIGER ERIC G ,  FITZSIMMONS JOHN A ,  GATES STEPHEN M

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/053