公开(公告)号：EP1856735A4

公开(公告)日：2009-07-15

申请号：EP06737610

申请日：2006-03-08

Applicant: IBM ,  SONY CORP

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A material stack (12) is provided comprising one or more films (14) that have a crack velocity of about IE- 10 m/sec or greater and at least one monolayer (16) within or in direct contact with the one or more films (14), wherein the at least one monolayer (16) reduces the crack velocity of the material stack (12) to a value of less than lE-10 m/sec. The one or more films ( 14) are not limited to low k dielectrics, but may include materials such as a metal. In a preferred embodiment, a low k dielectric stack (12) is provided, having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack (12) are improved by introducing at least one nanolayer (16) into the dielectric stack (12). The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of me films within the stack (12) and without the need of subjecting the inventive dielectric stack (12) to any post treatment steps.

公开(公告)号：EP1854131A4

公开(公告)日：2011-03-30

申请号：EP06849665

申请日：2006-01-12

Applicant: IBM

Inventor： DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

IPC: H01L21/20 ,  B05C11/00 ,  B32B3/26

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

公开(公告)号：WO2006096813A2

公开(公告)日：2006-09-14

申请号：PCT/US2006008449

申请日：2006-03-08

Applicant: IBM ,  SONY CORP ,  NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

IPC: H01L21/469 ,  H01L23/52 ,  H01L23/58

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A material stack (12) is provided comprising one or more films (14) that have a crack velocity of about IE- 10 m/sec or greater and at least one monolayer (16) within or in direct contact with the one or more films (14), wherein the at least one monolayer (16) reduces the crack velocity of the material stack (12) to a value of less than lE-10 m/sec. The one or more films ( 14) are not limited to low k dielectrics, but may include materials such as a metal. In a preferred embodiment, a low k dielectric stack (12) is provided, having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack (12) are improved by introducing at least one nanolayer (16) into the dielectric stack (12). The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of me films within the stack (12) and without the need of subjecting the inventive dielectric stack (12) to any post treatment steps.

Abstract translation: 提供材料堆叠（12），其包括一个或多个膜（14），其具有大约IE-10m / sec或更大的裂纹速度和至少一个单层（16）在一个或多个膜内或直接接触一个或多个膜 （14），其中所述至少一个单层（16）将所述材料堆叠（12）的裂纹速度降低到小于1E-10m / sec的值。 一个或多个膜（14）不限于低k电介质，而是可以包括诸如金属的材料。 在优选实施例中，提供具有约3.0或更小的有效介电常数k的低k电介质堆叠（12），其中通过引入至少一个纳米层（16）来提高堆叠（12）的机械性能 ）到介电叠层（12）中。 在不显着增加叠层（12）内的薄膜的介电常数并且不需要对本发明的电介质叠层（12）进行任何后处理步骤的情况下，实现机械性能的改善。

公开(公告)号：WO2007089223A3

公开(公告)日：2007-11-01

申请号：PCT/US2006001154

申请日：2006-01-12

Applicant: IBM ,  DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

Inventor： DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

IPC: H01L21/20 ,  B05C11/00 ,  B32B3/26

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Abstract translation: 描述了一种用于形成具有受控双轴应力的超低介电常数层的方法，其包括通过PECVD和旋涂涂覆之一形成含有Si，C，O和H的层并且在包含非常低浓度 的氧气和水每个小于10ppm。 还通过使用介电常数不超过2.8的方法来描述材料。 本发明克服了形成低双轴应力小于46MPa的薄膜的问题。

公开(公告)号：JP2006203197A

公开(公告)日：2006-08-03

申请号：JP2006007419

申请日：2006-01-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BRULEY JOHN ,  CARRUTHERS ROY A ,  LINN MARIE GIGNAC ,  HU CHAO-KUN ,  LINIGER ERIC G ,  MALHOTRA SANDRA G ,  ROSSNAGEL STEPHEN M

IPC: H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an improved on-chip Cu interconnection that uses a metal cap having a thickness of 1 to 5 nm.
SOLUTION: There is disclosed a procedure for coating the surface of a Cu Damascene wire with an element, having a thickness of 1 to 5 nm prior to deposition of an interlayer dielectric or dielectric diffusion barrier layer. The coating brings about protection against oxidization, increases the adhesive force between Cu and the dielectric, and makes the boundary surface diffusion of Cu reduced. Further, the thin cap layer increases the electromigration lifetime of Cu and reduces the occurrence of voids induced by stress. The selected element can be directly deposited on Cu embedded in the dielectric in the lower layer, without causing short-circuiting between the Cu wires. These selected elements are selected, based on the negative high reduction potential with respect to oxygen and water, low solubility to Cu, and the compound formation with Cu.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供使用厚度为1至5nm的金属帽的改进的片上Cu互连。 解决方案：公开了在沉积层间电介质或电介质扩散阻挡层之前，用具有1至5nm厚度的元件涂覆Cu镶嵌线的表面的步骤。 该涂层具有防氧化保护作用，增加了Cu与电介质之间的粘合力，使Cu的边界表面扩散减少。 此外，薄盖层增加了Cu的电迁移寿命并且减少了由应力引起的空隙的发生。 所选择的元件可以直接沉积在嵌入下层电介质中的Cu上，而不会导致Cu线之间的短路。 这些选择的元素基于相对于氧和水的负高还原电位，对Cu的低溶解度和与Cu的化合物形成而选择。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2001284453A

公开(公告)日：2001-10-12

申请号：JP2001033861

申请日：2001-02-09

Applicant: IBM

Inventor： JUDETH M RUBINO ,  JAHNES CHRISTOPHER ,  LINIGER ERIC G ,  RYAN JAMES G ,  CARLOS J SANBUSETEI ,  CARDONE FRANK ,  PURUSHOTHAMAN SAMPATH ,  PHIZHIMONS JOHN A ,  STEVEN M GATES

IPC: C22F1/10 ,  C22C19/00 ,  C22F1/00 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/76 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a low dielectric barrier with a superior diffusion characteristic for copper and adhesion, on a copper conductor. SOLUTION: A method comprises; 1) preparing a substrate having a copper conductor, 2) putting a metal alloy film including phosphor or boron as a protective layer, on the copper conductor, 3) carrying out the first annealing process to diffuse a metal alloy including phosphor or boron into 2-4 atom layers at least, on the top of the copper conductor, then 4) putting a dielectric film with low dielectric constant on the metal alloy film including phosphor or boron, and 5) carrying out the second annealing process. The obtained structure has a double layer barrier which includes the metal alloy film including phosphor or boron on the copper conductor and the dielectric material film on the metal alloy film, and shows superior barrier and adhesive characteristics for the copper conductor.

公开(公告)号：AU2002356887A1

公开(公告)日：2004-06-07

申请号：AU2002356887

申请日：2002-10-31

Applicant: IBM

Inventor： LANE MICHAEL W ,  LINIGER ERIC G ,  FITZSIMMONS JOHN A ,  GATES STEPHEN M

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/053