公开(公告)号：JP2002033313A

公开(公告)日：2002-01-31

申请号：JP2001161081

申请日：2001-05-29

Applicant: IBM

Inventor： NAEEM MUNIR D ,  MATHAD GANGADHARA S ,  KIM BYEONG YEOL ,  KUDELKA STEPHAN P ,  LEE BRIAN S ,  LI HONG ,  MORALES ELIZABETH ,  PARK YOUNG-JIN ,  RANADE RAJIV M

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method of minimizing an RIE lag, which occurs during production of a DT in a DRAM having a large aspect ratio. SOLUTION: Using this method, isotropic etching of a wafer can be prevented and hence a passivation film is formed to such a extent as to require to maintain a profile and shape of a DT in the wafer. The RIE process described here provides a partial DT etched in the wafer to attain a prescribed depth. This passivation film is grown to a certain thickness which is not sufficiently thick to block an opening of the deep-trench. In an alternative method, the passivation film is removed by a non-RIE process. The non-RIE process for removing the film may be wet etching using chemicals, such as hydrofluoric acid (buffered or unbuffered) or the like. Alternatively, a vapor phase of hydrofluoric anhydride or the like and/or un-ionized chemicals may be used. By controlling the film thickness, a prescribed depth of a DT for a high aspect ratio structure can be obtained.

公开(公告)号：JP2002050701A

公开(公告)日：2002-02-15

申请号：JP2001197112

申请日：2001-06-28

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： THOMAS W DAYER ,  LOUIS L SHEW ,  DAVID L KOTEKI ,  KARL J REEDENSU ,  GERHARD KUNKEL ,  LI HONG ,  YOUNG LIM ,  YON JIN PAKU

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM cell which eliminates critical photolithorgraphic fabrication steps by merging stacked capacitor construction with electrical contacts, and to provide a method of fabrication thereof. SOLUTION: It is sufficient to conduct in one lithography step to form electrical contacts, because the stacked capacitors are on the same plane as bit lines and the stacked capacitors are located in a insulating material provided between the bit lines. Unlike the conventional capacitor-over-bit line(COB) DRAM cells having the capacitors on the bit lines, this DRAM cell having capacitors adjacent to the bit lines eliminates the need to have dedicated contacts in the capacitor, making it possible to realize higher capacitance with lower global topography.

公开(公告)号：WO2006135810A2

公开(公告)日：2006-12-21

申请号：PCT/US2006022628

申请日：2006-06-09

Applicant: IBM ,  LI HONG ,  STANICH MIKEL JOHN ,  THOMPSON GERHARD R ,  WU CHAI WAH

Inventor： LI HONG ,  STANICH MIKEL JOHN ,  THOMPSON GERHARD R ,  WU CHAI WAH

IPC: G06K15/00 ,  H04N1/405

CPC classification number: H04N1/4055 ,  H04N1/40087

Abstract: A method and system for generating halftone tables, using a spot function, subdivides the pixels within the halftone cell of a halftone matrix into a plurality of sub-pixels, determines the value of the spot function corresponding to the position of each of the sub-pixels within the halftone matrix, repeats the subdividing and determining for all of the sub-pixels in the halftone matrix, ranks the values for the entire halftone matrix, normalizes the ranked values, generates a cumulative histogram based upon the normalized values, and stores the cumulative histogram as a halftone table.

Abstract translation: 使用点功能产生半色调表的方法和系统将半色调矩阵的半色调单元内的像素细分成多个子像素，确定与每个子像素的位置相对应的光点函数的值， 半色调矩阵内的像素重复细分和确定半色调矩阵中的所有子像素，对整个半色调矩阵的值进行排序，对排序的值进行归一化，基于归一化值生成累积直方图，并存储 累积直方图作为半色调表。