公开(公告)号：WO0193323A3

公开(公告)日：2002-06-27

申请号：PCT/US0115997

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NAEEM MUNIR D ,  LEE BRIAN S ,  MATHAD GANGADHARA S ,  LEE HEON ,  KIM BYEONG YEOL ,  MORALES ELIZABETH ,  KUDELKA STEPHAN P ,  RANADE RAJIV ,  PARK YOUNG-JIN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/311 ,  H01L21/8239

CPC classification number: H01L21/3081 ,  H01L21/3065

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., > 30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures

Abstract translation: 最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， > 30：1）。 该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。 所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。 允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。 或者，通过非RIE蚀刻工艺去除钝化膜。 可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。 膜的受控厚度允许实现高纵横比结构的预定DT深度

公开(公告)号：JP2002033313A

公开(公告)日：2002-01-31

申请号：JP2001161081

申请日：2001-05-29

Applicant: IBM

Inventor： NAEEM MUNIR D ,  MATHAD GANGADHARA S ,  KIM BYEONG YEOL ,  KUDELKA STEPHAN P ,  LEE BRIAN S ,  LI HONG ,  MORALES ELIZABETH ,  PARK YOUNG-JIN ,  RANADE RAJIV M

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method of minimizing an RIE lag, which occurs during production of a DT in a DRAM having a large aspect ratio. SOLUTION: Using this method, isotropic etching of a wafer can be prevented and hence a passivation film is formed to such a extent as to require to maintain a profile and shape of a DT in the wafer. The RIE process described here provides a partial DT etched in the wafer to attain a prescribed depth. This passivation film is grown to a certain thickness which is not sufficiently thick to block an opening of the deep-trench. In an alternative method, the passivation film is removed by a non-RIE process. The non-RIE process for removing the film may be wet etching using chemicals, such as hydrofluoric acid (buffered or unbuffered) or the like. Alternatively, a vapor phase of hydrofluoric anhydride or the like and/or un-ionized chemicals may be used. By controlling the film thickness, a prescribed depth of a DT for a high aspect ratio structure can be obtained.

公开(公告)号：JP2000269464A

公开(公告)日：2000-09-29

申请号：JP2000077068

申请日：2000-03-17

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： PARK YOUNG-JIN ,  RADENS CARL J ,  GERHARD KUNKEL

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To reduce an interference action between a buried strap and an access transistor channel of a semiconductor memory, by making a distance between a gate and the side of a trench larger than the minimum feature size. SOLUTION: A trench 102 forms an angle A at 0 degree to 45 degrees to a word line 104, and the angled portion 108 of an active area 106 forms a herringbone pattern to effectively lay out components such as the trench 102 and a contact 116. A portion 110 of the active area 106 is elongated to a value larger than feature size F to increase an average distance to reduce a dopant interference between the buried strap of the trench 102 and the word line 104. Therefore, this realizes a longer distance between the trench 102 and the bit line contact 116.

公开(公告)号：WO0154183A3

公开(公告)日：2002-02-28

申请号：PCT/US0101887

申请日：2001-01-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LEE HEON ,  PARK YOUNG-JIN ,  LIMB YOUNG ,  LEE BRIAN ,  LEE KILHO ,  ATHAVALE SATISH

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/316

CPC classification number: H01L28/75 ,  H01L27/10852 ,  H01L28/55

Abstract: In a method of forming a microelectronic structure of a Pt/BSTO/Pt capacitor stack for use in a DRAM device, the improvement comprising substantially eliminating or preventing oxygen out-diffusion from the BSTO material layer, comprising: preparing a bottom Pt electrode formation; subjecting the bottom Pt electrode formation to an oxygen plasma treatment to form an oxygen enriched Pt layer on the bottom Pt electrode; depositing a BSTO layer on said oxygen enriched Pt layer; depositing an upper Pt electrode layer on the BSTO layer; subjecting the upper Pt electrode layer to an oxygen plasma treatment to form an oxygen incorporated Pt layer; and depositing a Pt layer on the oxygen incorporated Pt layer upper Pt elect.

Abstract translation: 在形成用于DRAM器件的Pt / BSTO / Pt电容器堆叠的微电子结构的方法中，改进包括基本上消除或防止来自BSTO材料层的氧扩散，包括：制备底部Pt电极形成; 使底Pt电极形成氧等离子体处理，在底Pt电极上形成富氧Pt层; 在所述富氧Pt层上沉积BSTO层; 在BSTO层上沉积上部Pt电极层; 使上Pt电极层进行氧等离子体处理以形成掺入氧的Pt层; 并在掺有氧的Pt层上部Pt上沉积Pt层。