公开(公告)号：JP2002033313A

公开(公告)日：2002-01-31

申请号：JP2001161081

申请日：2001-05-29

Applicant: IBM

Inventor： NAEEM MUNIR D ,  MATHAD GANGADHARA S ,  KIM BYEONG YEOL ,  KUDELKA STEPHAN P ,  LEE BRIAN S ,  LI HONG ,  MORALES ELIZABETH ,  PARK YOUNG-JIN ,  RANADE RAJIV M

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method of minimizing an RIE lag, which occurs during production of a DT in a DRAM having a large aspect ratio. SOLUTION: Using this method, isotropic etching of a wafer can be prevented and hence a passivation film is formed to such a extent as to require to maintain a profile and shape of a DT in the wafer. The RIE process described here provides a partial DT etched in the wafer to attain a prescribed depth. This passivation film is grown to a certain thickness which is not sufficiently thick to block an opening of the deep-trench. In an alternative method, the passivation film is removed by a non-RIE process. The non-RIE process for removing the film may be wet etching using chemicals, such as hydrofluoric acid (buffered or unbuffered) or the like. Alternatively, a vapor phase of hydrofluoric anhydride or the like and/or un-ionized chemicals may be used. By controlling the film thickness, a prescribed depth of a DT for a high aspect ratio structure can be obtained.

公开(公告)号：JP2002367960A

公开(公告)日：2002-12-20

申请号：JP2002161955

申请日：2002-06-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MATHAD GANGADHARA S ,  PANDA SIDDHARTHA ,  RANADE RAJLV M

IPC: B44C1/22 ,  C03C25/68 ,  C23F1/00 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L21/30655 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/76224

Abstract: PROBLEM TO BE SOLVED: To provide a method of etching an opening having a high aspect ratio in a silicon substrate.
SOLUTION: This method comprises a process of etching a substrate with a first plasma formed using a first gas mixture including a bromo-contained gas, an oxygen-contained gas, and a first fluorine-contained gas. In this etching process, a side wall protecting attachment 24 is formed with the attachment accumulated near the entrance of an opening 14. In order to reduce the accumulation and increase the average etch rate, the side wall protecting attachment is made thinner periodically by forming a second plasma using a mixture containing silane and a second fluorine-contained gas. Over the entire process, the substrate is held in the same plasma reaction chamber, and the plasma is continuously retained in the process for making the side wall protecting attachment thinner. A trench having a depth larger than 40 times the width can be formed using a repetition cycle of etching and the process of making the side wall protecting attachment thinner.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种在硅衬底中蚀刻具有高纵横比的开口的方法。 解决方案：该方法包括使用包含含溴气体，含氧气体和第一含氟气体的第一气体混合物形成的第一等离子体来蚀刻基板的工艺。 在该蚀刻工艺中，形成侧壁保护附件24，其中附件积聚在开口14的入口附近。为了减少累积并增加平均蚀刻速率，侧壁保护附件通过形成 使用含有硅烷和第二含氟气体的混合物的第二等离子体。 在整个过程中，衬底保持在相同的等离子体反应室中，等离子体被连续地保留在使侧壁保护附着物更薄的过程中。 可以使用蚀刻的重复循环形成深度大于宽度的40倍的沟槽，并且使侧壁保护附着物的工艺变薄。

公开(公告)号：WO0193323A3

公开(公告)日：2002-06-27

申请号：PCT/US0115997

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NAEEM MUNIR D ,  LEE BRIAN S ,  MATHAD GANGADHARA S ,  LEE HEON ,  KIM BYEONG YEOL ,  MORALES ELIZABETH ,  KUDELKA STEPHAN P ,  RANADE RAJIV ,  PARK YOUNG-JIN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/311 ,  H01L21/8239

CPC classification number: H01L21/3081 ,  H01L21/3065

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., > 30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures

Abstract translation: 最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， > 30：1）。 该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。 所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。 允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。 或者，通过非RIE蚀刻工艺去除钝化膜。 可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。 膜的受控厚度允许实现高纵横比结构的预定DT深度

公开(公告)号：DE10224935A1

公开(公告)日：2002-12-19

申请号：DE10224935

申请日：2002-06-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MATHAD GANGADHARA S ,  PANDA SIDDHARTHA ,  RANADE RAJLV M

IPC: B44C1/22 ,  C03C25/68 ,  C23F1/00 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762

Abstract: A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.

公开(公告)号：DE102004012241A1

公开(公告)日：2004-10-28

申请号：DE102004012241

申请日：2004-03-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： MATHAD GANGADHARA S ,  RANADE RAJIV M ,  CHAN KEVIN K ,  KULKARNI SUBHASH B

IPC: H01L21/205 ,  H01L21/334 ,  H01L21/763 ,  H01L21/8242 ,  H01L21/762

公开(公告)号：CA1260365A

公开(公告)日：1989-09-26

申请号：CA505365

申请日：1986-03-27

Applicant: IBM

Inventor： CHEN LEE ,  MATHAD GANGADHARA S

IPC: H01L21/302 ,  H01L21/3065 ,  C30B33/00 ,  H01L21/467

Abstract: FI9-83-090 ANISOTROPIC SILICON ETCHING IN FLUORINATED PLASMA A method of high rate anisotropic etching of silicon in a high pressure plasma is described. In one embodiment, the etching ambient is a mixture of either NF3 or SF6, an inert gas such as nitrogen, and a polymerizing gas such as CHF3 that creates conditions necessary for anisotropy not normally possible with nonpolymerizing fluorinated gases in a high pressure regime. The etch process is characterized by high etch rates and good uniformity utilizing photoresist or similar materials as a mask. The present process may advantageously be used to etch deep trenches in silicon using a photoresist mask.

公开(公告)号：CA1261785A

公开(公告)日：1989-09-26

申请号：CA504799

申请日：1986-03-24

Applicant: IBM

Inventor： CHEN LEE ,  MATHAD GANGADHARA S

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  C23F1/02 ,  C23F1/12 ,  H01L21/308

Abstract: METHOD FOR ETCH PROFILE CONTROL A method for precisely controlling the profile of an opening etched in a layer of material, for example, an insulating layer. In one embodiment, wherein a silicon dioxide layer is reactive ion etched through a photoresist mask, the reactive species is changed during the etching process to change the slope of the opening, the upper sidewall portion of the opening having a shallow slope and the lower sidewall portion of the opening having a steep slope.