公开(公告)号：DE69618386T2

公开(公告)日：2002-09-26

申请号：DE69618386

申请日：1996-05-07

Applicant: TOSHIBA KAWASAKI KK ,  IBM

Inventor： LICATA THOMAS JOHN ,  NUNES RONALD WAYNE ,  OKAZAKI MOTOYA

IPC: H01L23/538 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768

Abstract: A process for forming a dual-damascene interconnect employs a spun-on organic layer above an interlayer dielectric having a set of apertures for vias that forms tapered regions about the apertures without penetrating the apertures. The slope of the tapered regions is transferred during the etching process to form self-aligned tapered vias. A silicon substrate (10) over which an oxide or other insulating layer (110) is first formed. A layer first level of metal interconnect (120) and a layer of SiO2 (130) are formed insequent onto the structure, then an aperture (140) extending down to and stopping on metal interconnect layer is formed. Now an anti-reflective coating (ARC) layer (135) is put down and spun onto the structure. Unexpectedly, the surface tension of the ARC layer prevents the ARC material from getting into the aperture but forms a tapered rim at its edge (as illustrated). After baking the ARC layer, a layer of resist (150) is deposited, exposed, and developed to form a novel aperture (142). An non-isotropic etch using CF4/O2 chemistry as the etching gas is performed, then both the resist and ARC layer are stripped. The result is an aperture having a tapered bottom selection which, when filled with metal (147/147) and polished to become level with the top of SiO2 layer produces the chemical Damascene interconnect.

公开(公告)号：SG42979A1

公开(公告)日：1997-10-17

申请号：SG1996001715

申请日：1992-03-31

Applicant: IBM

Inventor： LEE PEI-ING PAUL ,  LICATA THOMAS JOHN ,  MCDEVITT THOMAS LEDDY ,  PARRIES PAUL CHRISTIAN ,  PENNINGTON SCOTT LEWIS ,  RYAN JAMES GARDINER ,  STRIPPE DAVID CRAIG

IPC: C23C14/04 ,  H01L21/203 ,  C23C14/46 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H05K3/40

Abstract: A sputtering deposition wherein high aspect ratio apertures (50) are coated with conductive films (40) exhibiting low bulk resistivity, low impurity concentrations, and regular morphologies. A collimator (60) is used having an aspect ratio that approximates the aspect ratio of the apertures (50). The resulting film thickness at the bottom of the aperture is at least 2X what can be achieved using conventional sputtering methods.

公开(公告)号：DE69618386D1

公开(公告)日：2002-02-14

申请号：DE69618386

申请日：1996-05-07

Applicant: TOSHIBA KAWASAKI KK ,  IBM

Inventor： LICATA THOMAS JOHN ,  NUNES RONALD WAYNE ,  OKAZAKI MOTOYA

IPC: H01L23/538 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768

Abstract: A process for forming a dual-damascene interconnect employs a spun-on organic layer above an interlayer dielectric having a set of apertures for vias that forms tapered regions about the apertures without penetrating the apertures. The slope of the tapered regions is transferred during the etching process to form self-aligned tapered vias. A silicon substrate (10) over which an oxide or other insulating layer (110) is first formed. A layer first level of metal interconnect (120) and a layer of SiO2 (130) are formed insequent onto the structure, then an aperture (140) extending down to and stopping on metal interconnect layer is formed. Now an anti-reflective coating (ARC) layer (135) is put down and spun onto the structure. Unexpectedly, the surface tension of the ARC layer prevents the ARC material from getting into the aperture but forms a tapered rim at its edge (as illustrated). After baking the ARC layer, a layer of resist (150) is deposited, exposed, and developed to form a novel aperture (142). An non-isotropic etch using CF4/O2 chemistry as the etching gas is performed, then both the resist and ARC layer are stripped. The result is an aperture having a tapered bottom selection which, when filled with metal (147/147) and polished to become level with the top of SiO2 layer produces the chemical Damascene interconnect.

公开(公告)号：DE69415476T2

公开(公告)日：1999-07-15

申请号：DE69415476

申请日：1994-10-06

Applicant: IBM

Inventor： GEISS PETER JOHN ,  LICATA THOMAS JOHN ,  HO HERBERT LEI ,  RYAN JAMES GARDNER

IPC: H01L21/28 ,  C30B1/00 ,  H01L21/223 ,  H01L21/225 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  C30B29/10 ,  C30B1/02

Abstract: A process for forming an epitaxial cobalt silicide (CoSi2) film in a semiconductor device, comprises: (a) forming on the Si substrate (10) a layer of refractory metal (12) comprising W, Cr, Mo or mixts. or silicides thereof; (b) forming a Co layer (14); and (c) annealing the Co layer at a temp. high enough to form epitaxial CosI2 film (16) overlying the substrate. A process for forming epitaxial CoSi2 by forming a W layer, followed by a Co layer, on a Si substrate, followed by annealing at 550[deg]C. for a time long enough to form epitaxial CoSi2.

公开(公告)号：DE69415476D1

公开(公告)日：1999-02-04

申请号：DE69415476

申请日：1994-10-06

Applicant: IBM

Inventor： GEISS PETER JOHN ,  LICATA THOMAS JOHN ,  HO HERBERT LEI ,  RYAN JAMES GARDNER

IPC: H01L21/28 ,  C30B1/00 ,  H01L21/223 ,  H01L21/225 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  C30B29/10 ,  C30B1/02

Abstract: A process for forming an epitaxial cobalt silicide (CoSi2) film in a semiconductor device, comprises: (a) forming on the Si substrate (10) a layer of refractory metal (12) comprising W, Cr, Mo or mixts. or silicides thereof; (b) forming a Co layer (14); and (c) annealing the Co layer at a temp. high enough to form epitaxial CosI2 film (16) overlying the substrate. A process for forming epitaxial CoSi2 by forming a W layer, followed by a Co layer, on a Si substrate, followed by annealing at 550[deg]C. for a time long enough to form epitaxial CoSi2.