公开(公告)号：EP0762498A3

公开(公告)日：1998-06-24

申请号：EP96305678

申请日：1996-08-01

Applicant: IBM ,  SIEMENS AG

Inventor： LEE PEI-ING PAUL ,  KLAASEN WILLIAM ALAN ,  MITWALSKY ALEXANDER

IPC: H01H85/00 ,  H01L21/82 ,  H01L23/525 ,  H01L23/58

CPC classification number: H01L23/5258 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse window (110) structure and method for forming the same for a semiconductor device with a fuse (102) and a cutting site on the fuse, the structure having (1) a first oxide region (116) substantially in register with the cutting site, the first oxide region having a first thickness, (2) a second oxide region (118) substantially in register with a first land generally surrounding the cutting site, the first land generally in register with the fuse, the second region having a second thickness, and (3) a third oxide region (120) substantially in register with a second land generally surrounding the fuse (102), the third region having a third thickness different than the first thickness.
Different fuse window structures are formed by using etch stops (106,108) with different configurations, each configuration differing with regard to coverage of the three oxide regions.

Abstract translation: 一种用于在具有熔丝（102）和熔丝上的切割位置的半导体器件上形成熔丝窗口（110）的结构和方法，所述结构具有（1）基本上与切割对准的第一氧化物区域（116） 第一氧化物区域具有第一厚度，（2）第二氧化物区域（118）基本上与通常围绕切割位置的第一焊盘对齐，第一焊盘通常与熔丝对准，第二区域具有第二厚度 （3）与通常围绕熔丝（102）的第二焊盘基本对准的第三氧化物区域（120），第三区域具有不同于第一厚度的第三厚度。 通过使用具有不同配置的蚀刻停止件（106,108）来形成不同的熔丝窗口结构，每种配置在三个氧化物区域的覆盖方面不同。

公开(公告)号：DE69314679T2

公开(公告)日：1998-04-02

申请号：DE69314679

申请日：1993-02-25

Applicant: SIEMENS AG ,  IBM

Inventor： COTE WILLIAM JOSEPH ,  LEE PEI-ING PAUL ,  SANDWICK THOMAS EDWIN ,  VOLLMER BERND MICHAEL ,  VYNORIUS VICTOR ,  WOLFF STUART HOWARD

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/41

Abstract: Electrically conducting vias and lines are created by a three step process. First, a controlled amount of a soft, low resistivity metal (12) is deposited in a trench or hole to a point below the top surface of the dielectric (10) in which the trench or hole is formed. Subsequently, the low resistivity metal (12) is overcoated with a hard metal (16) such as CVD tungsten. Finally, chemical-mechanical polishing is used to planarize the structure. The hard metal (16) serves the function of protecting the low resistivity metal (12) from scratches and corrosion which would ordinarily be encountered if the low resistivity metal were subjected to the harsh chemical-mechanical polishing slurries. An ideal method for partially filling trenches or holes in a substrate is by sputtering at elevated temperatures such that metallization at the bottom of a trench or hole separates from metallization on a top surface adjacent the trench or hole. An etchback procedure may also be used to separate metallization in a trench or hole from metallization adjacent a trench or hole. Trenchs and holes may also be filled by selective deposition. In addition, trenches and holes may also be lined by a metal liner (18) prior to metallization (12) deposition which can serve as a diffusion barrier.

公开(公告)号：DE19620549C2

公开(公告)日：1998-08-27

申请号：DE19620549

申请日：1996-05-22

Applicant: IBM

Inventor： LEE PEI-ING PAUL ,  PREIN FRANK

IPC: B23K26/00 ,  H01L21/302 ,  H01L21/461 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108

Abstract: In an integrated circuit having interconnecting lines formed on an insulated layer deposited on a semiconductor substrate which provide connections between elements integral to the integrated circuit, a fuse structure programmable by a laser beam that includes: a melt-away elongated fuse link joining two segments of an interconnecting line; a plurality of fins integral and coplanar to the fuse link, each of the fins transversally extending away from the fuse link for absorbing energy emitted by the laser beam; and a reflecting plate positioned underneath the fuse link to reflect energy provided by the laser beam back into the fuse link, such that both the combination of the fins and the reflecting plate reduces the energy emitted by the laser beam required to blow the fuse structure.

公开(公告)号：AT159615T

公开(公告)日：1997-11-15

申请号：AT93102979

申请日：1993-02-25

Applicant: SIEMENS AG ,  IBM

Inventor： COTE WILLIAM JOSEPH ,  LEE PEI-ING PAUL ,  SANDWICK THOMAS EDWIN ,  VOLLMER BERND MICHAEL ,  VYNORIUS VICTOR ,  WOLFF STUART HOWARD

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/41

Abstract: Electrically conducting vias and lines are created by a three step process. First, a controlled amount of a soft, low resistivity metal (12) is deposited in a trench or hole to a point below the top surface of the dielectric (10) in which the trench or hole is formed. Subsequently, the low resistivity metal (12) is overcoated with a hard metal (16) such as CVD tungsten. Finally, chemical-mechanical polishing is used to planarize the structure. The hard metal (16) serves the function of protecting the low resistivity metal (12) from scratches and corrosion which would ordinarily be encountered if the low resistivity metal were subjected to the harsh chemical-mechanical polishing slurries. An ideal method for partially filling trenches or holes in a substrate is by sputtering at elevated temperatures such that metallization at the bottom of a trench or hole separates from metallization on a top surface adjacent the trench or hole. An etchback procedure may also be used to separate metallization in a trench or hole from metallization adjacent a trench or hole. Trenchs and holes may also be filled by selective deposition. In addition, trenches and holes may also be lined by a metal liner (18) prior to metallization (12) deposition which can serve as a diffusion barrier.

公开(公告)号：DE69314679D1

公开(公告)日：1997-11-27

申请号：DE69314679

申请日：1993-02-25

Applicant: SIEMENS AG ,  IBM

Inventor： COTE WILLIAM JOSEPH ,  LEE PEI-ING PAUL ,  SANDWICK THOMAS EDWIN ,  VOLLMER BERND MICHAEL ,  VYNORIUS VICTOR ,  WOLFF STUART HOWARD

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/41

Abstract: Electrically conducting vias and lines are created by a three step process. First, a controlled amount of a soft, low resistivity metal (12) is deposited in a trench or hole to a point below the top surface of the dielectric (10) in which the trench or hole is formed. Subsequently, the low resistivity metal (12) is overcoated with a hard metal (16) such as CVD tungsten. Finally, chemical-mechanical polishing is used to planarize the structure. The hard metal (16) serves the function of protecting the low resistivity metal (12) from scratches and corrosion which would ordinarily be encountered if the low resistivity metal were subjected to the harsh chemical-mechanical polishing slurries. An ideal method for partially filling trenches or holes in a substrate is by sputtering at elevated temperatures such that metallization at the bottom of a trench or hole separates from metallization on a top surface adjacent the trench or hole. An etchback procedure may also be used to separate metallization in a trench or hole from metallization adjacent a trench or hole. Trenchs and holes may also be filled by selective deposition. In addition, trenches and holes may also be lined by a metal liner (18) prior to metallization (12) deposition which can serve as a diffusion barrier.

公开(公告)号：DE19620549A1

公开(公告)日：1996-12-12

申请号：DE19620549

申请日：1996-05-22

Applicant: IBM

Inventor： LEE PEI-ING PAUL ,  PREIN FRANK

IPC: B23K26/00 ,  H01L21/302 ,  H01L21/461 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108

Abstract: The melting spot structure in an integrated circuit coupler transverse coupling lines forming on an insulating layer on a semiconductor substrate for connections between elements of the integrated circuit. An elongated, metal rated melting spot coupler two segments of an intermediate coupling line. It has an integral finger, coupled in coplanar manner to the rated melting spot, from which it extends transversely for energy retaining, radiated from the laser beam. It reduces the laser energy required for melting the melting spot structure.

公开(公告)号：DE69114346D1

公开(公告)日：1995-12-14

申请号：DE69114346

申请日：1991-04-13

Applicant: IBM

Inventor： CRONIN JOHN EDWARD ,  KAANTA CARTER WELLING ,  PREVITI-KELLY ROSEMARY ANN ,  RYAN JAMES GARDNER ,  LEE PEI-ING PAUL ,  YOON JUNG HOON

IPC: C08G73/10 ,  G03F7/038 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/46 ,  H01L23/485

公开(公告)号：DE3872579D1

公开(公告)日：1992-08-13

申请号：DE3872579

申请日：1988-04-08

Applicant: IBM

Inventor： CRONIN JOHN EDWARD ,  LEE PEI-ING PAUL

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/90 ,  H01L23/52

公开(公告)号：HK1001601A1

公开(公告)日：1998-06-26

申请号：HK98100235

申请日：1998-01-12

Applicant: SIEMENS AG ,  IBM

Inventor： COTE WILLIAM JOSEPH ,  LEE PEI-ING PAUL ,  SANDWICK THOMAS EDWIN ,  VOLLMER BERND MICHAEL ,  VYNORIUS VICTOR ,  WOLFF STUART HOWARD

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/41 ,  H01L

Abstract: Electrically conducting vias and lines are created by a three step process. First, a controlled amount of a soft, low resistivity metal (12) is deposited in a trench or hole to a point below the top surface of the dielectric (10) in which the trench or hole is formed. Subsequently, the low resistivity metal (12) is overcoated with a hard metal (16) such as CVD tungsten. Finally, chemical-mechanical polishing is used to planarize the structure. The hard metal (16) serves the function of protecting the low resistivity metal (12) from scratches and corrosion which would ordinarily be encountered if the low resistivity metal were subjected to the harsh chemical-mechanical polishing slurries. An ideal method for partially filling trenches or holes in a substrate is by sputtering at elevated temperatures such that metallization at the bottom of a trench or hole separates from metallization on a top surface adjacent the trench or hole. An etchback procedure may also be used to separate metallization in a trench or hole from metallization adjacent a trench or hole. Trenchs and holes may also be filled by selective deposition. In addition, trenches and holes may also be lined by a metal liner (18) prior to metallization (12) deposition which can serve as a diffusion barrier.

公开(公告)号：SG42979A1

公开(公告)日：1997-10-17

申请号：SG1996001715

申请日：1992-03-31

Applicant: IBM

Inventor： LEE PEI-ING PAUL ,  LICATA THOMAS JOHN ,  MCDEVITT THOMAS LEDDY ,  PARRIES PAUL CHRISTIAN ,  PENNINGTON SCOTT LEWIS ,  RYAN JAMES GARDINER ,  STRIPPE DAVID CRAIG

IPC: C23C14/04 ,  H01L21/203 ,  C23C14/46 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H05K3/40

Abstract: A sputtering deposition wherein high aspect ratio apertures (50) are coated with conductive films (40) exhibiting low bulk resistivity, low impurity concentrations, and regular morphologies. A collimator (60) is used having an aspect ratio that approximates the aspect ratio of the apertures (50). The resulting film thickness at the bottom of the aperture is at least 2X what can be achieved using conventional sputtering methods.