公开(公告)号：EP2024995A4

公开(公告)日：2013-07-03

申请号：EP07797764

申请日：2007-05-25

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L21/764 ,  H01L21/76283

公开(公告)号：EP1825508A4

公开(公告)日：2009-06-24

申请号：EP05852638

申请日：2005-12-01

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

公开(公告)号：EP1831925A4

公开(公告)日：2009-06-24

申请号：EP05852637

申请日：2005-12-01

Applicant: IBM

Inventor： FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

IPC: H01L21/8238

CPC classification number: H01L21/823835

Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).

公开(公告)号：WO2006060575A2

公开(公告)日：2006-06-08

申请号：PCT/US2005043474

申请日：2005-12-01

Applicant: IBM ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

Abstract translation: 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在半导体衬底（102）中形成用于容纳第一类型半导体器件（130）的第一阱区（103）; 在所述半导体衬底（102）中形成用于容纳第二类型半导体器件（140）的第二阱区（104）; 用掩模（114）屏蔽所述第一类型半导体器件（130）; 在所述第二类型半导体器件（140）上沉积第一金属层（118）; 在所述第二类型半导体器件（140）上执行第一自对准硅化物形成; 去除所述面罩（114）; 在第一和第二类型半导体器件（130,140）上沉积第二金属层（123）; 以及在所述第一类型半导体器件（130）上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同的自杀材料的过程。

公开(公告)号：WO2006060574A3

公开(公告)日：2006-07-20

申请号：PCT/US2005043473

申请日：2005-12-01

Applicant: IBM ,  FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

Inventor： FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

IPC: H01L21/8238

CPC classification number: H01L21/823835

Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).

Abstract translation: 一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅极的方法，其中该方法包括在半导体衬底（252）中形成具有第一阱区（253）的第一类型半导体器件（270） ，第一阱区（253）中的第一源极/漏极硅化物区域（266）以及与第一源极/漏极硅化物区域（266）隔离的第一类型栅极（263）; 形成具有半导体衬底（252）中的第二阱区（254），第二阱区（254）中的第二源极/漏极硅化物区（256）和第二类型栅极（258）的第二类型半导体器件 ）与第二源极/漏极硅化物区域（256）隔离; 在所述第二类型半导体器件（280）上方选择性地形成第一金属层（218）; 仅在所述第二类型栅极（258）上执行第一全硅化物（FUSI）栅极形成; 在第一和第二类型半导体器件（270,280）上沉积第二金属层（275）; 以及仅在第一类型栅极（263）上执行第二FUSI栅极形成。

公开(公告)号：WO2007140288A3

公开(公告)日：2008-04-24

申请号：PCT/US2007069720

申请日：2007-05-25

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

Inventor： CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

IPC: H01L21/76

CPC classification number: H01L21/764 ,  H01L21/76283

Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrates having device regions (2, 4, 6), each comprises a base semiconductor substrate layer (12) and a semiconductor device layer (16) and a buried insulator layer (14) between. The semiconductor device layer (16) supported by vertical insulating pillars (22), each having a ledge extending between the base semiconductor substrate layer (12) and the semiconductor device layer (16). The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a "floating" semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap (15) and is supported by the vertical insulating pillars (22). The air gap (15) is preferably formed by selective removal of a sacrificial layer (13) located between the base semiconductor substrate layer (12) and the semiconductor device layer (16).

Abstract translation: 本发明涉及具有器件区域（2,4,6）的绝缘体上绝缘体（SOI）衬底，每个衬底半导体衬底层（12）和半导体器件层（16）和掩埋绝缘体层（14） ）之间。 由垂直绝缘柱（22）支撑的半导体器件层（16）各自具有在基底半导体衬底层（12）和半导体器件层（16）之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙（15）与基底半导体衬底层间隔开并由垂直绝缘柱（ 22）。 气隙（15）优选通过选择性地去除位于基底半导体衬底层（12）和半导体器件层（16）之间的牺牲层（13）来形成。