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1.发明专利
公开(公告)号：JP2003218177A
公开(公告)日：2003-07-31
申请号：JP2003008636
申请日：2003-01-16
Applicant: IBM
Inventor： MAGERLEIN JOHN HAROLD , MCKNIGHT SAMUEL ROY , PETRARCA KEVIN SHAWN , PURUSHOTHAMAN SAMPATH , SAMBUCETTI CARLOS JUAN , VAN HORN JOSEPH J , VOLANT RICHARD PAUL , WALKER GEORGE FREDERICK
Abstract: PROBLEM TO BE SOLVED: To provide an ability to test and 'burn in' device chips that require ultra high pitch I/O pads. SOLUTION: A system for testing a collection of the device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; the carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JP2003273158A
公开(公告)日：2003-09-26
申请号：JP2003003619
申请日：2003-01-09
Inventor： FURMAN BRUCE KENNETH , SURENDRA MAHESWARAN , GOMA SHERIF A , KARECKI ANNA , KARECKI SIMON M , MAGERLEIN JOHN HAROLD , PETRARCA KEVIN SHAWN , PURUSHOTHAMAN SAMPATH , SAMBUCETTI CARLOS JUAN , VOLANT RICHARD PAUL , WALKER GEORGE FREDERICK
IPC: H01L23/52 , H01L21/288 , H01L21/3205 , H01L21/60 , H05K1/03 , H05K1/11 , H05K3/38
CPC classification number: H01L24/12 , H01L21/288 , H01L21/2885 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0401 , H01L2224/05571 , H01L2224/05599 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/1308 , H01L2224/13083 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/13169 , H01L2224/13582 , H01L2224/13616 , H01L2224/13644 , H01L2224/13655 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H05K1/0306 , H05K1/112 , H05K3/388 , H05K2201/0317 , H05K2201/09472 , H05K2201/09509 , H05K2201/10674 , H01L2224/45111 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
Abstract: PROBLEM TO BE SOLVED: To provide a system making an interconnection with a quite high density by connecting device chips and a chip carrier by using a microjoint interconnect structure.
SOLUTION: In the system, a pair of device chips is mounted on a microjoint interconnect chip carrier by using a microjoint interconnect structure. The microjoint interconnect chip carrier comprises a multilayer substrate having a plurality of receptacles on its surface. A pair of microjoint interconnect pads corresponding to the receptacles is provided on the device chips. Interconnecting wiring enabling an interconnection between the device chips is provided between the receptacles.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：通过使用微型连接互连结构，通过连接器件芯片和芯片载体来提供使密度相当高的互连的系统。 解决方案：在系统中，通过使用微型连接互连结构将一对器件芯片安装在微型连接互连芯片载体上。 微型连接互连芯片载体包括其表面上具有多个插座的多层基板。 在器件芯片上设置一对对应于插座的微接点互连焊盘。 在插座之间设置能够实现器件芯片之间的互连的互连布线。 版权所有（C）2003，JPO
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公开(公告)号：WO9706444A1
公开(公告)日：1997-02-20
申请号：PCT/US9612544
申请日：1996-08-09
Applicant: IBM
Inventor： LEAS JAMES MARC , KOSS ROBERT WILLIAM , VAN HORN JODY JOHN , WALKER GEORGE FREDERICK , PERRY CHARLES HAMPTON , GARDELL DAVID LEWIS , DINGLE STEVE LEO , PRILIK RONALD
IPC: G01R1/06 , G01R1/073 , G01R31/28 , H01L21/66 , G01R31/316
CPC classification number: G01R1/07385 , G01R1/07314 , G01R31/2863 , G01R31/2879 , G01R31/2886 , G01R31/2889
Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the products chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.
Abstract translation: 用于在产品晶片上的所有集成电路芯片中同时测试或燃烧的装置和方法。 该装置包括具有测试芯片的玻璃陶瓷载体和用于连接到产品晶片上的大量芯片的焊盘的装置。 测试芯片上的稳压器提供了产品芯片上的电源和电源焊盘之间的接口，每个产品芯片至少有一个电压调节器。 电压调节器向产品芯片提供指定的Vdd电压，由此Vdd电压基本上与产品芯片所消耗的电流无关。 电压调节器或其他电子装置限制电流到任何产品芯片，如果它有一个短。 电压调节器电路可以是门控和可变的，并且其可以具有延伸到产品芯片的传感器线路。 测试芯片还可以提供测试功能，例如测试模式和用于存储测试结果的寄存器。
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4.发明专利
公开(公告)号：AU2002363902A8
公开(公告)日：2003-07-30
申请号：AU2002363902
申请日：2002-12-19
Applicant: IBM
Inventor： PETRARCA KEVIN SHAWN , SAMBUCETTI CARLOS JUAN , PURUSHOTHAMAN SAMPATH , VOLANT RICHARD PAUL , MAGERLEIN JOHN HAROLD , WALKER GEORGE FREDERICK
IPC: H01L21/60 , H01L21/00 , H01L23/485 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/34 , H05K3/38
Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
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公开(公告)号：DE69323270D1
公开(公告)日：1999-03-11
申请号：DE69323270
申请日：1993-10-18
Applicant: IBM
Inventor： FREIERMUTH PETER EDWARD , GINN KATHLEEN SCOTT , HALEY JEFFREY ALAN , LAMAIRE SUSAN JARVIS , LEWIS DAVID ANDREW , MILLS GAVIN TERENCE , REDMOND TIMOTHY ALVIDA , TSANG YUK LUN , VAN HORN JOSEPH JOHN , VIEHBECK ALFRED , WALKER GEORGE FREDERICK , YANG JER-MING , LONG CLARENCE SANFORD
IPC: G01R31/26 , G01R31/28 , G01R31/311 , H01L21/265 , H01L21/268 , H01L21/326 , H01L21/329 , H01L21/00
Abstract: The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of rectifying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.
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Patent Agency Ranking
公开(公告)号：AT176333T
公开(公告)日：1999-02-15
申请号：AT93116795
申请日：1993-10-18
Applicant: IBM
Inventor： FREIERMUTH PETER EDWARD , GINN KATHLEEN SCOTT , HALEY JEFFREY ALAN , LAMAIRE SUSAN JARVIS , LEWIS DAVID ANDREW , MILLS GAVIN TERENCE , REDMOND TIMOTHY ALVIDA , TSANG YUK LUN , VAN HORN JOSEPH JOHN , VIEHBECK ALFRED , WALKER GEORGE FREDERICK , YANG JER-MING , LONG CLARENCE SANFORD
IPC: G01R31/26 , G01R31/28 , G01R31/311 , H01L21/265 , H01L21/268 , H01L21/326 , H01L21/329 , H01L21/00
Abstract: The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of rectifying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.
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公开(公告)号：DE69218078D1
公开(公告)日：1997-04-17
申请号：DE69218078
申请日：1992-08-10
Applicant: IBM
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8.发明专利
公开(公告)号：CA2472750C
公开(公告)日：2009-02-03
申请号：CA2472750
申请日：2002-12-19
Applicant: IBM
Inventor： VOLANT RICHARD PAUL , SAMBUCETTI CARLOS JUAN , PURUSHOTHAMAN SAMPATH , PETRARCA KEVIN SHAWN , WALKER GEORGE FREDERICK , MAGERLEIN JOHN HAROLD
IPC: H01L21/60 , H01L21/00 , H01L23/485 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/34 , H05K3/38
Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer , barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer an d a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
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公开(公告)号：DE69323270T2
公开(公告)日：1999-08-12
申请号：DE69323270
申请日：1993-10-18
Applicant: IBM
Inventor： FREIERMUTH PETER EDWARD , GINN KATHLEEN SCOTT , HALEY JEFFREY ALAN , LAMAIRE SUSAN JARVIS , LEWIS DAVID ANDREW , MILLS GAVIN TERENCE , REDMOND TIMOTHY ALVIDA , TSANG YUK LUN , VAN HORN JOSEPH JOHN , VIEHBECK ALFRED , WALKER GEORGE FREDERICK , YANG JER-MING , LONG CLARENCE SANFORD
IPC: G01R31/26 , G01R31/28 , G01R31/311 , H01L21/265 , H01L21/268 , H01L21/326 , H01L21/329 , H01L21/00
Abstract: The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of rectifying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.
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公开(公告)号：PL318978A1
公开(公告)日：1997-07-21
申请号：PL31897895
申请日：1995-08-08
Applicant: IBM
Inventor： BRADY MICHAEL JOHN , COFINO THOMAS , HEINRICH HARLEY KENT , JOHNSON GLEN WALDEN , MOSKOWITZ PAUL ANDREW , WALKER GEORGE FREDERICK
IPC: H01Q1/40 , G01V15/00 , G06K19/077 , H01Q1/22 , H01Q7/00 , H01Q9/16 , H01Q21/26 , H01Q21/28 , H04B1/38 , H04B1/59
Abstract: A radiofrequency identification tag has a semiconductor chip with radio frequency circuit, logic, memory circuits, and further includes an antenna that is mounted on a substrate. The antenna may be used by the chip to modulate an incident RF signal to transfer information to a base station. The antenna comprises one or more lengths of thin wire that are connected directly to the chip by means of wire bonding. The chip and antenna combination can be sealed with an organic film covering.
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