公开(公告)号：JP2004336780A

公开(公告)日：2004-11-25

申请号：JP2004135747

申请日：2004-04-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： PIERSON MARK V ,  SCHENFELD EUGEN

IPC: H04B10/12 ,  G02B6/26 ,  G02B6/43 ,  H04B10/13 ,  H04B10/135 ,  H04B10/14

CPC classification number: G02B6/43

Abstract: PROBLEM TO BE SOLVED: To provide more simplified techniques for optimizing the throughput of an integrated circuit mounted on a light cube and inputting/outputting an electric signal with the integrated circuit mounted on the light cube. SOLUTION: A first optical transmitter chip and a first optical receiver chip are mounted on one surface of the light cube. A first consecutive printed circuit board is soldered on conductive surfaces of the first optical transmitter chip and the first optical receiver chip on the opposite side of the light cube. A second optical transmitter chip and a second optical receiver chip are mounted on the opposite surface of the light cube. A second consecutive printed circuit board is soldered on conductive surfaces of the second optical transmitter chip and the second optical receiver chip on the opposite side of the light cube. The first optical transmitter chip is optically aligned with the second optical receiver chip via the light cube. The second optical transmitter chip is optically aligned with the first optical receiver chip via the light cube. The first and second printed circuit boards are bent by 90° to be soldered on the other printed circuit board or to be connected to an edge connector on the other printed circuit board. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JPH1115014A

公开(公告)日：1999-01-22

申请号：JP8965498

申请日：1998-04-02

Applicant: IBM

Inventor： PIERSON MARK V

IPC: G02F1/1347 ,  G02F1/13 ,  G02F1/1333 ,  G02F1/1345 ,  G09F9/40

Abstract: PROBLEM TO BE SOLVED: To provide a wiring mutually connecting method which is of relatively inexpensive and is of simple and which enables a display having an increased visual field area in the liquid crystal planar panel display provided with plural liquid crystal display tiles which are arranged in a matrix and are fixed to tile carries. SOLUTION: Adjacent liquid crystal display tiles are electrically mutually connected in the inside of a device, thereby wiring escapes are obtained in pixels of the tiles. That is, an intertile interconnection 5 is formed, thereby a pixel wiring escape extending to surrounding of a tile display for horizontal address lines 6 and vertical address lines 7 is obtained. Then, even the center tile 8 is connected to adjacent tile wirings by the intertile interconnection in this manner and vertical pixel wirings 10 and horizontal pixel wirings can be both run.

公开(公告)号：JPH10270835A

公开(公告)日：1998-10-09

申请号：JP6967198

申请日：1998-03-19

Applicant: IBM

Inventor： GREGG JOSEPH ARUMETSUTSUAANI ,  ROBERT NICHOLAS IVES ,  PIERSON MARK V ,  TERRY ALAN TULL

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K1/00 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To reduce deformation while using a mask reflow technology, by mounting a plurality of modules on a carrier by solder balls, which are on the first major surface of the flexible film carrier and are mutually connected to mutually connecting solder pads. SOLUTION: An electronic package includes a flexible film carrier 1 which has electronic circuits on the both major surfaces. The flexible film carrier 1 is made of a dielectric material, which may be thermoplastic resin or thermosetting organic resin. On a first major flat plate of the flexible film carrier 1, a plurality of interconnecting solder pads 8 are provided. Solder mask material 5 is arranged on the major surface of the flexible film crrier, and a solder mask layer 6 is arranged on a second major surface. A region without a solder mask 5 exists between the adjoining modules to be mounted later on the first major surface. Then, the module 2 having a solder ball 9 is mounted.

公开(公告)号：ID24794A

公开(公告)日：2000-08-16

申请号：ID991157

申请日：1999-12-20

Applicant: IBM

Inventor： EGITTO FRANK D ,  GAYNES MICHAEL A ,  KODNANI RAMESH ,  MATIONSO LUIS J ,  PIERSON MARK V

IPC: B29C59/14 ,  H01L21/56 ,  D03D11/00

公开(公告)号：DE3770556D1

公开(公告)日：1991-07-11

申请号：DE3770556

申请日：1987-09-01

Applicant: IBM

Inventor： PIERSON MARK V

IPC: H01R12/04 ,  B21K25/00 ,  H01L21/48 ,  H01R43/04 ,  H01R43/20 ,  H05K3/30

公开(公告)号：CA2120557A1

公开(公告)日：1994-12-12

申请号：CA2120557

申请日：1994-04-05

Applicant: IBM

Inventor： ANSCHEL MORRIS ,  INGRAHAM ANTHONY P ,  LAMB CHARLES R ,  LOWELL MICHAEL D ,  MARKOVICH VOYA R ,  MAYR WOLFGANG ,  MURPHY RICHARD G ,  PIERSON MARK V ,  POWERS TAMAR A ,  RENY TIMOTHY S ,  REYNOLDS SCOTT D ,  SAMMAKIA BAHGAT G ,  STORR WAYNE R

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01R13/02

Abstract: METHOD AND APPARATUS FOR TESTING OF INTEGRATED CIRCUIT CHIPS A method of testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip test fixture system is provided. The chip test fixture system has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into electrically conductive contact with the conductor pads on the chip test fixture system. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing the chip is removed from the substrate.