公开(公告)号：DE10334946A1

公开(公告)日：2004-03-18

申请号：DE10334946

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  CHUDZIK MICHAEL PATRICK ,  RAJARAO JAMMY ,  DIVAKARUNI RAMACHANDRA

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

公开(公告)号：DE10258201B4

公开(公告)日：2008-07-03

申请号：DE10258201

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： RAJARAO JAMMY ,  KUDELKA STEPHAN ,  MACSTAY IRENE ,  RAHN STEPHEN ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/8242

公开(公告)号：DE10334946B4

公开(公告)日：2006-03-09

申请号：DE10334946

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  CHUDZIK MICHAEL PATRICK ,  RAJARAO JAMMY ,  DIVAKARUNI RAMACHANDRA

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

公开(公告)号：SG94845A1

公开(公告)日：2003-03-18

申请号：SG200103937

申请日：2001-06-28

Applicant: IBM

Inventor： LAWRENCE ALFRED CLEVENGER ,  JACK ALLAN MANDELMAN ,  RAJARAO JAMMY ,  OLEG GLUSCHENKOV ,  IRENE LENNOX MCSTAY ,  KWONG-HON WONG ,  JONATHAN FALTERMEIER

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: A gate structure is disclosed for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer 14 on a semiconductor substrate 12, over which a polysilicon gate electrode 16 is formed. The gate structure further includes a gate conductor 18 that is electrically connected with the gate electrode through a diffusion barrier layer 20 having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.