公开(公告)号：JPH1154454A

公开(公告)日：1999-02-26

申请号：JP19988497

申请日：1997-07-25

Applicant: IBM

Inventor： CABRAL JR CYRIL ,  LAWRENCE ALFRED CLEVENGER ,  FRANCOIS MAXDOLE ,  HARPER JAMES M E ,  MANN RANDY W ,  GLENN LESTER MILES ,  NAKOS JAMES S ,  RONEN ANDREW ROY ,  CATHERINE L SAENGER

IPC: C22C14/00 ,  C30B3/00 ,  H01L21/28

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for forming a C54 phase titanium silicide without requiring a second high-temperature annealing. SOLUTION: A low resistivity titanium silicide and semiconductor devices incorporating the same are formed by a titanium alloy comprising titanium and 1-20 atom percent refractory metal deposited in a layer overlying a silicon substrate. The substrate is then heated to a temperature which is sufficient to practically form a C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, but more preferably be Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900 deg.C, and more preferably between about 600 to 700 deg.C.

公开(公告)号：JP2002016070A

公开(公告)日：2002-01-18

申请号：JP2001171050

申请日：2001-06-06

Applicant: IBM

Inventor： LAWRENCE ALFRED CLEVENGER ,  RONALD JEAN PHILIPPI ,  RODBELL KENNETH PARKER ,  ROY CHARLES IGGULDEN ,  CHAOKUN FUU ,  LINN MARIE GIGNAC ,  WEBER STEPHAN ,  GAMBINO JEFFREY PETER ,  SCHNABEL RAINER FLORIAN

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a dual damascene process that can reliably form aluminum interconnection exhibiting improved electro migration characteristics, as compared with aluminum interconnection that is formed by the conventional RIE technique. SOLUTION: More specifically, the dual damascene process depends on a PVD-Ti/CVD-TiN barrier layer and forms an aluminum line showing great reduction in a saturation resistance level, the inhibition of the electro migration, or both of them especially in a line longer than 100 micrometers. The electromigration life time of the dual damascene aluminum line depends greatly on the conditions of materials and material-filling processes. When there is deviation in the materials and treatment, the electromigration life time way possibly become shorter than life time that is achieved by an aluminum RIE interconnection line, and this becomes a serious matter.

公开(公告)号：SG94845A1

公开(公告)日：2003-03-18

申请号：SG200103937

申请日：2001-06-28

Applicant: IBM

Inventor： LAWRENCE ALFRED CLEVENGER ,  JACK ALLAN MANDELMAN ,  RAJARAO JAMMY ,  OLEG GLUSCHENKOV ,  IRENE LENNOX MCSTAY ,  KWONG-HON WONG ,  JONATHAN FALTERMEIER

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: A gate structure is disclosed for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer 14 on a semiconductor substrate 12, over which a polysilicon gate electrode 16 is formed. The gate structure further includes a gate conductor 18 that is electrically connected with the gate electrode through a diffusion barrier layer 20 having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.

公开(公告)号：SG104330A1

公开(公告)日：2004-06-21

申请号：SG200203152

申请日：2002-05-24

Applicant: IBM

Inventor： CYRIL CABRAL JR ,  LAWRENCE ALFRED CLEVENGER ,  LOUIS HSU ,  KEITH KWONG HON WONG

IPC: C23C14/00 ,  C23C14/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

Abstract: A method for forming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.