公开(公告)号：WO0223586A3

公开(公告)日：2002-06-27

申请号：PCT/US0128440

申请日：2001-09-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ATHAVALE SATISH ,  LEE BRIAN ,  LEE HEON ,  LEE KILHO ,  LIMB YOUNG ,  PARK YOUNG JIN ,  SIM JAI-HOON

IPC: H01J37/32

CPC classification number: H01J37/32412 ,  H01J37/32706 ,  H01J2237/334

Abstract: Apparatus for etching a patterned layer of a noble metal such as platinum. The apparatus implements a process whereby exposed areas of the noble metal are first implanted with ions and are subsequently etched. Both the ion implantation step and the etching step occur sequentially in the same chamber in the presence of a plasma discharge. The apparatus uses either a dual output power supply or two distinct power supplies to sequentially supply a high power output required for the ion implantation step and a low power output required for the etching step. Multiple cycles of implantation followed by etching may be applied to achieve deep etching of thick layers. A programmed computer controls the process steps. A method of using the apparatus is also provided.

Abstract translation: 蚀刻贵金属如铂的图案化层的设备。 该设备实施一种方法，由此首先将贵金属的暴露区域注入离子并随后进行蚀刻。 在存在等离子体放电的情况下，离子注入步骤和蚀刻步骤在相同的腔室中顺序地发生。 该装置使用双输出电源或两个不同的电源来顺序地提供离子注入步骤所需的高功率输出和蚀刻步骤所需的低功率输出。 可以应用多次注入之后的蚀刻以实现厚层的深刻蚀。 编程的计算机控制过程步骤。 还提供了使用该设备的方法。

公开(公告)号：JP2002222873A

公开(公告)日：2002-08-09

申请号：JP2001388866

申请日：2001-12-21

Applicant: IBM

Inventor： RAMACHANDORA DEIVAKARUNI ,  LEE HEON ,  MANDELMAN JACK A ,  RADENS CARL J ,  SIM JAI-HOON

IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/772

Abstract: PROBLEM TO BE SOLVED: To provide an improved method of forming a vertical MOSFET structure. SOLUTION: A method of forming a semiconductor memory cell array structure comprises a process of providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer 22 planarized up to the top surface of a trench top oxide 24 on a silicon substrate, a process of forming a recess 39 in the gate conductor layer below the top surface of the silicon substrate, a process of forming doping pockets 46 in an array P well 32 by implanting N-type dopant species through the recess at an angle, a process of forming spacers 44 on the side wall of the recess by depositing an oxide layer in the recess and then etching the oxide layer, and a process of depositing a gate conductor material in the recess and then planarizing the gate conductor material up to the top surface of the trench top oxide.