公开(公告)号：WO0193323A3

公开(公告)日：2002-06-27

申请号：PCT/US0115997

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NAEEM MUNIR D ,  LEE BRIAN S ,  MATHAD GANGADHARA S ,  LEE HEON ,  KIM BYEONG YEOL ,  MORALES ELIZABETH ,  KUDELKA STEPHAN P ,  RANADE RAJIV ,  PARK YOUNG-JIN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/311 ,  H01L21/8239

CPC classification number: H01L21/3081 ,  H01L21/3065

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., > 30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures

Abstract translation: 最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， > 30：1）。 该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。 所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。 允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。 或者，通过非RIE蚀刻工艺去除钝化膜。 可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。 膜的受控厚度允许实现高纵横比结构的预定DT深度

公开(公告)号：WO0203423A3

公开(公告)日：2002-08-08

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供了一种DRAM单元和制造方法，其通过将堆叠的电容器形成与电触点并入来消除关键的光刻制造步骤。 由于层叠的电容器（46,48,50）与位线（36）是共面的，所以单个光刻步骤可用于形成电触点（28），并且堆叠的电容器位于设置在 位线。 与常规的电容器位线（COB）DRAM单元不同，这种位线旁边的DRAM电池消除了将触点专用于电容器的需要，使得可以在较低的全局地形下实现更高的电容。

公开(公告)号：WO0223586A3

公开(公告)日：2002-06-27

申请号：PCT/US0128440

申请日：2001-09-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ATHAVALE SATISH ,  LEE BRIAN ,  LEE HEON ,  LEE KILHO ,  LIMB YOUNG ,  PARK YOUNG JIN ,  SIM JAI-HOON

IPC: H01J37/32

CPC classification number: H01J37/32412 ,  H01J37/32706 ,  H01J2237/334

Abstract: Apparatus for etching a patterned layer of a noble metal such as platinum. The apparatus implements a process whereby exposed areas of the noble metal are first implanted with ions and are subsequently etched. Both the ion implantation step and the etching step occur sequentially in the same chamber in the presence of a plasma discharge. The apparatus uses either a dual output power supply or two distinct power supplies to sequentially supply a high power output required for the ion implantation step and a low power output required for the etching step. Multiple cycles of implantation followed by etching may be applied to achieve deep etching of thick layers. A programmed computer controls the process steps. A method of using the apparatus is also provided.

Abstract translation: 蚀刻贵金属如铂的图案化层的设备。 该设备实施一种方法，由此首先将贵金属的暴露区域注入离子并随后进行蚀刻。 在存在等离子体放电的情况下，离子注入步骤和蚀刻步骤在相同的腔室中顺序地发生。 该装置使用双输出电源或两个不同的电源来顺序地提供离子注入步骤所需的高功率输出和蚀刻步骤所需的低功率输出。 可以应用多次注入之后的蚀刻以实现厚层的深刻蚀。 编程的计算机控制过程步骤。 还提供了使用该设备的方法。

公开(公告)号：JP2002222873A

公开(公告)日：2002-08-09

申请号：JP2001388866

申请日：2001-12-21

Applicant: IBM

Inventor： RAMACHANDORA DEIVAKARUNI ,  LEE HEON ,  MANDELMAN JACK A ,  RADENS CARL J ,  SIM JAI-HOON

IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/772

Abstract: PROBLEM TO BE SOLVED: To provide an improved method of forming a vertical MOSFET structure. SOLUTION: A method of forming a semiconductor memory cell array structure comprises a process of providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer 22 planarized up to the top surface of a trench top oxide 24 on a silicon substrate, a process of forming a recess 39 in the gate conductor layer below the top surface of the silicon substrate, a process of forming doping pockets 46 in an array P well 32 by implanting N-type dopant species through the recess at an angle, a process of forming spacers 44 on the side wall of the recess by depositing an oxide layer in the recess and then etching the oxide layer, and a process of depositing a gate conductor material in the recess and then planarizing the gate conductor material up to the top surface of the trench top oxide.

公开(公告)号：WO0203423A8

公开(公告)日：2002-04-11

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts because the stacked capacitors are co-planar with the bit lines and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供DRAM单元和制造方法，其通过将堆叠的电容器结构与电触点合并来消除关键的光刻制造步骤。 因为堆叠的电容器与位线共面并且堆叠的电容器位于位线之间提供的绝缘材料中，所以可以使用单个光刻步骤来形成电触点。 与传统的电容器位线（COB）DRAM单元不同，这种位于电容器旁边的位线DRAM单元消除了对电容器专用接触的需要，使得可以用较低的全局地形实现更高的电容。

公开(公告)号：WO0154183A3

公开(公告)日：2002-02-28

申请号：PCT/US0101887

申请日：2001-01-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LEE HEON ,  PARK YOUNG-JIN ,  LIMB YOUNG ,  LEE BRIAN ,  LEE KILHO ,  ATHAVALE SATISH

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/316

CPC classification number: H01L28/75 ,  H01L27/10852 ,  H01L28/55

Abstract: In a method of forming a microelectronic structure of a Pt/BSTO/Pt capacitor stack for use in a DRAM device, the improvement comprising substantially eliminating or preventing oxygen out-diffusion from the BSTO material layer, comprising: preparing a bottom Pt electrode formation; subjecting the bottom Pt electrode formation to an oxygen plasma treatment to form an oxygen enriched Pt layer on the bottom Pt electrode; depositing a BSTO layer on said oxygen enriched Pt layer; depositing an upper Pt electrode layer on the BSTO layer; subjecting the upper Pt electrode layer to an oxygen plasma treatment to form an oxygen incorporated Pt layer; and depositing a Pt layer on the oxygen incorporated Pt layer upper Pt elect.

Abstract translation: 在形成用于DRAM器件的Pt / BSTO / Pt电容器堆叠的微电子结构的方法中，改进包括基本上消除或防止来自BSTO材料层的氧扩散，包括：制备底部Pt电极形成; 使底Pt电极形成氧等离子体处理，在底Pt电极上形成富氧Pt层; 在所述富氧Pt层上沉积BSTO层; 在BSTO层上沉积上部Pt电极层; 使上Pt电极层进行氧等离子体处理以形成掺入氧的Pt层; 并在掺有氧的Pt层上部Pt上沉积Pt层。

公开(公告)号：DE10219841A1

公开(公告)日：2003-02-13

申请号：DE10219841

申请日：2002-05-03

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： PARK YOUNGJIN ,  COSTRINI GREG ,  KOTECKI DAVID E ,  LEE HEON

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/283

Abstract: Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.

公开(公告)号：DE10219841B4

公开(公告)日：2007-11-29

申请号：DE10219841

申请日：2002-05-03

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： PARK YOUNGJIN ,  COSTRINI GREG ,  KOTECKI DAVID E ,  LEE HEON

IPC: H01L21/283 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

Abstract: Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.