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    GATE STACKS
    2.
    发明公开
    GATE STACKS 有权
    GATESTAPEL

    公开(公告)号：EP1805798A4

    公开(公告)日：2009-08-05

    申请号：EP05812439

    申请日：2005-09-30

    Applicant: IBM

    Inventor： MARTIN DALE W ,  SHANK STEVEN M ,  TRIPLETT MICHAEL C ,  TUCKER DEBORAH A

    IPC: H01L23/48 ,  H01L21/302 ,  H01L21/336 ,  H01L21/469 ,  H01L21/4763

    CPC classification number: H01L21/28247 ,  H01L21/28035 ,  H01L29/4916 ,  Y10S257/90

    Abstract: A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate (110). The method comprises (a) forming a gate dielectric layer (120) on top of the substrate (110), (b) forming a gate polysilicon layer (130) on top of the gate dielectric layer (120), (c) implanting n-type dopants in a top layer (130a) of the gate polysilicon layer (130), (d) etching away portions of the gate polysilicon layer (130) and the gate dielectric layer (120) so as to form a gate stack (132, 134, 122) on the substrate (110), and (e) thermally oxidizing side walls of the gate stack (132, 134, 122) with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer (170) is formed at the same depth in the polysilicon material of the gate stack (132, 134, 122) regardless of the doping concentration. Therefore, the n-type doped region (132) of the gate stack has the same width as that of the undoped region (134) of the gate stack (132, 134, 122.).

    Abstract translation: 用于在半导体衬底（110）中限定源极/漏极区域的栅极叠层的结构和制造方法。 该方法包括：（a）在衬底（110）的顶部上形成栅极介电层（120），（b）在栅极介电层（120）的顶部上形成栅极多晶硅层（130），（c） （130）的顶层（130a）中，（d）蚀刻掉栅极多晶硅层（130）和栅极介电层（120）的部分以形成栅极叠层（132） （110）上，并且（e）在存在载氮气体的情况下热氧化栅叠层（132,134,122）的侧壁。 结果，不管掺杂浓度如何，在栅极叠层（132,134,122）的多晶硅材料中以相同的深度形成扩散阻挡层（170）。 因此，栅极堆叠的n型掺杂区域（132）具有与栅极堆叠（132,134,122）的未掺杂区域（134）相同的宽度。

    DEUTERIUM SUBSTANCE FOR USE IN SEMICONDUCTOR TREATMENT
    3.
    发明专利
    DEUTERIUM SUBSTANCE FOR USE IN SEMICONDUCTOR TREATMENT 失效

    公开(公告)号：JPH1187712A

    公开(公告)日：1999-03-30

    申请号：JP19272598

    申请日：1998-07-08

    Applicant: IBM

    Inventor： CLARK WILLIAM F ,  FERENCE THOMAS G ,  HOOK TERENCE B ,  MARTIN DALE W

    IPC: H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/30 ,  H01L21/316 ,  H01L21/318 ,  H01L21/324 ,  H01L21/336

    Abstract: PROBLEM TO BE SOLVED: To ensure strong resistance against hot electron effect on the interface of silicon/silicon dioxide while suppressing damage of an element by substituting deuterium for hydrogen of a film formation reactive substance being used in production of semiconductor thereby producing a deuterium film substance at the time of film formation. SOLUTION: A MOSFET element 100 comprises a single crystal silicon substrate 11, source-drain regions 12, 13, a gate oxide 14, a gate polysilicon 15, a gate sidewall spacer 16, a silicon nitride barrier wall 18, a passive oxide layer (e.g. SiO2 ) to be bonded, and a self-aligned silicate layer 17. These components of gate oxide 14, polysilicon 15, or the like, in the element contain hydrogen molecules emitted into the oxide during annealing process. The hydrogen atom is substituted by deuterium at the time of film formation to produce a deuterium film substance. Hydrogen migrates to the interface of silicon/silicon dioxide of these component of element to produce a deuterium substance thus exhibiting resistance against heat cycle.

    GATE STACKS
    5.
    发明申请
    GATE STACKS 审中-公开
    门盖板

    公开(公告)号：WO2006039632A3

    公开(公告)日：2006-08-10

    申请号：PCT/US2005035455

    申请日：2005-09-30

    Applicant: IBM ,  MARTIN DALE W ,  SHANK STEVEN M ,  TRIPLETT MICHAEL C ,  TUCKER DEBORAH A

    Inventor： MARTIN DALE W ,  SHANK STEVEN M ,  TRIPLETT MICHAEL C ,  TUCKER DEBORAH A

    IPC: H01L23/48 ,  H01L21/302 ,  H01L21/336 ,  H01L21/469 ,  H01L21/4763

    CPC classification number: H01L21/28247 ,  H01L21/28035 ,  H01L29/4916 ,  Y10S257/90

    Abstract: A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate (110). The method comprises (a) forming a gate dielectric layer (120) on top of the substrate (110), (b) forming a gate polysilicon layer (130) on top of the gate dielectric layer (120), (c) implanting n-type dopants in a top layer (130a) of the gate polysilicon layer (130), (d) etching away portions of the gate polysilicon layer (130) and the gate dielectric layer (120) so as to form a gate stack (132, 134, 122) on the substrate (110), and (e) thermally oxidizing side walls of the gate stack (132, 134, 122) with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer (170) is formed at the same depth in the polysilicon material of the gate stack (132, 134, 122) regardless of the doping concentration. Therefore, the n-type doped region (132) of the gate stack has the same width as that of the undoped region (134) of the gate stack (132, 134, 122.).

    Abstract translation: 一种用于限定半导体衬底（110）中的源极/漏极区域的栅堆叠的结构和制造方法。 该方法包括：（a）在衬底（110）的顶部上形成栅极电介质层（120），（b）在栅极电介质层（120）的顶部上形成栅极多晶硅层（130），（c） 栅极多晶硅层（130）的顶层（130a）中的（d）型掺杂剂，（d）蚀刻掉栅极多晶硅层（130）和栅极电介质层（120）的部分，以形成栅叠层 ，134,122），以及（e）在存在含氮气体的情况下热氧化所述栅堆叠（132,134,122）的侧壁。 结果，不管掺杂浓度如何，在栅极堆叠（132,134,122）的多晶硅材料中的相同深度处形成扩散阻挡层（170）。 因此，栅极堆叠的n型掺杂区域（132）具有与栅极叠层（132,134,122。）的未掺杂区域（134）相同的宽度。

    Abgeflachte Substratoroberfläche für ein Bonden eines Substrats
    7.
    发明专利
    Abgeflachte Substratoroberfläche für ein Bonden eines Substrats 未知

    公开(公告)号：DE112012004106T5

    公开(公告)日：2014-07-10

    申请号：DE112012004106

    申请日：2012-08-03

    Applicant: IBM

    Inventor： COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETH-ANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

    IPC: H01L21/60 ,  H01L21/58 ,  H01L23/48

    Abstract: Verfahren zum Bonden von Substratoberflächen, gebondete Substratanordnungen sowie Entwurfsstrukturen für eine gebondete Substratanordnung. Es werden Einheiten-Strukturen (18, 19, 20, 21) eines Produkt-Chips (25) unter Verwendung einer ersten Oberfläche (15) eines Einheiten-Substrats (10) gebildet. Auf dem Produkt-Chip wird eine Verdrahtungsschicht (26) einer Zwischenverbindungsstruktur für die Einheiten-Strukturen gebildet. Die Verdrahtungsschicht wird planarisiert. Ein provisorischer Handhabungswafer (52) wird entfernbar an die planarisierte Verdrahtungsschicht gebondet. In Reaktion auf das entfernbare Bonden des provisorischen Handhabungswafers an die planarisierte erste Verdrahtungsschicht wird eine zweite Oberfläche (54) des Einheiten-Substrats, die entgegengesetzt zu der ersten Oberfläche ist, an ein endgültiges Handhabungssubstrat (56) gebondet. Anschließend wird der provisorische Handhabungswafer von der Anordnung entfernt.

    Flattened substrate surface for substrate bonding
    9.
    发明专利
    Flattened substrate surface for substrate bonding 未知

    公开(公告)号：GB2509683A

    公开(公告)日：2014-07-09

    申请号：GB201408711

    申请日：2012-08-03

    Applicant: IBM

    Inventor： COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETH-ANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

    Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.

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