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    METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS
    2.
    发明申请
    METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS 审中-公开
    用于形成CMOS图像传感器的抗反射结构的方法

    公开(公告)号：WO2009140099A3

    公开(公告)日：2010-01-21

    申请号：PCT/US2009042766

    申请日：2009-05-05

    Applicant: IBM ,  ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

    Inventor： ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

    IPC: H01L31/112

    CPC classification number: H01L27/14685 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14689 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

    Abstract translation: 具有小于由光电二极管（8）可检测的光的波长范围的垂直（h）和横向（p）尺寸的凸起（5）形成在具有不同折射率的两个层之间的光学界面处。 突起可以通过使用在第二聚合物嵌段组分（111）的基体内形成第一聚合物嵌段组分（112）的亚光刻特征阵列的自组装嵌段共聚物来形成。 聚合物嵌段组分的图案被转移到第一光学层（4）中以形成纳米级突起的阵列。 或者，可以使用常规光刻来形成尺寸小于光的波长的突起。 第二光学层直接形成在第一光学层的突起上。 第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

    Abgeflachte Substratoroberfläche für ein Bonden eines Substrats
    3.
    发明专利
    Abgeflachte Substratoroberfläche für ein Bonden eines Substrats 未知

    公开(公告)号：DE112012004106T5

    公开(公告)日：2014-07-10

    申请号：DE112012004106

    申请日：2012-08-03

    Applicant: IBM

    Inventor： COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETH-ANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

    IPC: H01L21/60 ,  H01L21/58 ,  H01L23/48

    Abstract: Verfahren zum Bonden von Substratoberflächen, gebondete Substratanordnungen sowie Entwurfsstrukturen für eine gebondete Substratanordnung. Es werden Einheiten-Strukturen (18, 19, 20, 21) eines Produkt-Chips (25) unter Verwendung einer ersten Oberfläche (15) eines Einheiten-Substrats (10) gebildet. Auf dem Produkt-Chip wird eine Verdrahtungsschicht (26) einer Zwischenverbindungsstruktur für die Einheiten-Strukturen gebildet. Die Verdrahtungsschicht wird planarisiert. Ein provisorischer Handhabungswafer (52) wird entfernbar an die planarisierte Verdrahtungsschicht gebondet. In Reaktion auf das entfernbare Bonden des provisorischen Handhabungswafers an die planarisierte erste Verdrahtungsschicht wird eine zweite Oberfläche (54) des Einheiten-Substrats, die entgegengesetzt zu der ersten Oberfläche ist, an ein endgültiges Handhabungssubstrat (56) gebondet. Anschließend wird der provisorische Handhabungswafer von der Anordnung entfernt.

    DELAMINATION AND CRACK RESISTANT IMAGE SENSOR STRUCTURES AND METHODS
    5.
    发明专利
    DELAMINATION AND CRACK RESISTANT IMAGE SENSOR STRUCTURES AND METHODS 未知

    公开(公告)号：CA2719684A1

    公开(公告)日：2009-12-10

    申请号：CA2719684

    申请日：2009-06-04

    Applicant: IBM

    Inventor： JAFFE MARK D ,  GAMBINO JEFFREY P ,  LEIDY ROBERT K ,  MUSANTE CHARLES F ,  RASSEL RICHARD J

    IPC: H01L27/00

    Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer (22) with respect to a planarizing layer (18) within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer (20') of different dimensions than active lens layer (20) located over a circuitry portion (Rl) of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture (A) within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion (Rl) within the particular image sensor structures.

    METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS
    6.
    发明专利
    METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS 未知

    公开(公告)号：CA2719681A1

    公开(公告)日：2009-11-19

    申请号：CA2719681

    申请日：2009-05-05

    Applicant: IBM

    Inventor： ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

    IPC: H01L31/112 ,  H01L31/0236

    Abstract: Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

    METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS
    7.
    发明专利
    METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS 未知

    公开(公告)号：CA2719681C

    公开(公告)日：2018-03-13

    申请号：CA2719681

    申请日：2009-05-05

    Applicant: IBM

    Inventor： ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

    IPC: H01L31/18 ,  H01L21/77 ,  H01L27/146

    Abstract: Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

    Flattened substrate surface for substrate bonding
    8.
    发明专利
    Flattened substrate surface for substrate bonding 未知

    公开(公告)号：GB2509683A

    公开(公告)日：2014-07-09

    申请号：GB201408711

    申请日：2012-08-03

    Applicant: IBM

    Inventor： COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETH-ANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

    Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.

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