公开(公告)号：JP2003218177A

公开(公告)日：2003-07-31

申请号：JP2003008636

申请日：2003-01-16

Applicant: IBM

Inventor： MAGERLEIN JOHN HAROLD ,  MCKNIGHT SAMUEL ROY ,  PETRARCA KEVIN SHAWN ,  PURUSHOTHAMAN SAMPATH ,  SAMBUCETTI CARLOS JUAN ,  VAN HORN JOSEPH J ,  VOLANT RICHARD PAUL ,  WALKER GEORGE FREDERICK

IPC: G01R31/26 ,  G01R1/04 ,  H01L21/60 ,  H01L21/66 ,  H05K3/24 ,  H05K3/32

Abstract: PROBLEM TO BE SOLVED: To provide an ability to test and 'burn in' device chips that require ultra high pitch I/O pads. SOLUTION: A system for testing a collection of the device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; the carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003273158A

公开(公告)日：2003-09-26

申请号：JP2003003619

申请日：2003-01-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： FURMAN BRUCE KENNETH ,  SURENDRA MAHESWARAN ,  GOMA SHERIF A ,  KARECKI ANNA ,  KARECKI SIMON M ,  MAGERLEIN JOHN HAROLD ,  PETRARCA KEVIN SHAWN ,  PURUSHOTHAMAN SAMPATH ,  SAMBUCETTI CARLOS JUAN ,  VOLANT RICHARD PAUL ,  WALKER GEORGE FREDERICK

IPC: H01L23/52 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/60 ,  H05K1/03 ,  H05K1/11 ,  H05K3/38

CPC classification number: H01L24/12 ,  H01L21/288 ,  H01L21/2885 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13582 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2224/45111 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: PROBLEM TO BE SOLVED: To provide a system making an interconnection with a quite high density by connecting device chips and a chip carrier by using a microjoint interconnect structure.
SOLUTION: In the system, a pair of device chips is mounted on a microjoint interconnect chip carrier by using a microjoint interconnect structure. The microjoint interconnect chip carrier comprises a multilayer substrate having a plurality of receptacles on its surface. A pair of microjoint interconnect pads corresponding to the receptacles is provided on the device chips. Interconnecting wiring enabling an interconnection between the device chips is provided between the receptacles.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：通过使用微型连接互连结构，通过连接器件芯片和芯片载体来提供使密度相当高的互连的系统。 解决方案：在系统中，通过使用微型连接互连结构将一对器件芯片安装在微型连接互连芯片载体上。 微型连接互连芯片载体包括其表面上具有多个插座的多层基板。 在器件芯片上设置一对对应于插座的微接点互连焊盘。 在插座之间设置能够实现器件芯片之间的互连的互连布线。 版权所有（C）2003，JPO

公开(公告)号：JP2011079311A

公开(公告)日：2011-04-21

申请号：JP2010224565

申请日：2010-10-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JONES BRADLEY P ,  KNICKERBOCKER SARAH H ,  VOLANT RICHARD PAUL

IPC: B29C33/38

CPC classification number: H01L24/742 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/11003 ,  H01L2224/131 ,  H01L2924/1431 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K3/3478 ,  H01L2924/014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for making a mold with a protective layer.
SOLUTION: The method for making the mold with the protective layer includes making a mold base plate having at least one substantially flat surface, accumulating a mold protective material layer on at least one substantially flat surface, and etching a plurality of cavities on at least one substantially flat surface through the mold protective layer.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造具有保护层的模具的方法。 用于制造具有保护层的模具的方法包括制造具有至少一个基本上平坦的表面的模具基板，在至少一个基本上平坦的表面上积聚模具保护材料层，并且在多个腔体上蚀刻多个空腔 通过模具保护层的至少一个基本平坦的表面。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：CA2472750C

公开(公告)日：2009-02-03

申请号：CA2472750

申请日：2002-12-19

Applicant: IBM

Inventor： VOLANT RICHARD PAUL ,  SAMBUCETTI CARLOS JUAN ,  PURUSHOTHAMAN SAMPATH ,  PETRARCA KEVIN SHAWN ,  WALKER GEORGE FREDERICK ,  MAGERLEIN JOHN HAROLD

IPC: H01L21/60 ,  H01L21/00 ,  H01L23/485 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/38

Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer , barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer an d a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

公开(公告)号：AU2002363902A8

公开(公告)日：2003-07-30

申请号：AU2002363902

申请日：2002-12-19

Applicant: IBM

Inventor： PETRARCA KEVIN SHAWN ,  SAMBUCETTI CARLOS JUAN ,  PURUSHOTHAMAN SAMPATH ,  VOLANT RICHARD PAUL ,  MAGERLEIN JOHN HAROLD ,  WALKER GEORGE FREDERICK

IPC: H01L21/60 ,  H01L21/00 ,  H01L23/485 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/38

Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

公开(公告)号：AU2002363902A1

公开(公告)日：2003-07-30

申请号：AU2002363902

申请日：2002-12-19

Applicant: IBM

Inventor： MAGERLEIN JOHN HAROLD ,  PETRARCA KEVIN SHAWN ,  PURUSHOTHAMAN SAMPATH ,  SAMBUCETTI CARLOS JUAN ,  VOLANT RICHARD PAUL ,  WALKER GEORGE FREDERICK

IPC: H01L21/60 ,  H01L21/00 ,  H01L23/485 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/38

Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

公开(公告)号：CA2472750A1

公开(公告)日：2003-07-24

申请号：CA2472750

申请日：2002-12-19

Applicant: IBM

Inventor： WALKER GEORGE FREDERICK ,  VOLANT RICHARD PAUL ,  MAGERLEIN JOHN HAROLD ,  SAMBUCETTI CARLOS JUAN ,  PURUSHOTHAMAN SAMPATH ,  PETRARCA KEVIN SHAWN

IPC: H01L21/60 ,  H01L21/00 ,  H01L23/485 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/38

Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.