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    High bandwidth module
    1.
    发明专利
    High bandwidth module 未知

    公开(公告)号：AU2021235527A1

    公开(公告)日：2022-08-25

    申请号：AU2021235527

    申请日：2021-02-18

    Applicant: IBM

    Inventor： ARVIN CHARLES LEON ,  SINGH BHUPENDER ,  LI SHIDONG ,  MUZZY CHRIS ,  WASSICK THOMAS ANTHONY

    IPC: H01L21/66 ,  H01L21/822

    Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

    Halbleiterstruktur mit Passivierung durch Versatz zur Verringerung der Elektromigration
    2.
    发明专利
    Halbleiterstruktur mit Passivierung durch Versatz zur Verringerung der Elektromigration 未知

    公开(公告)号：DE102012103571A1

    公开(公告)日：2012-11-22

    申请号：DE102012103571

    申请日：2012-04-24

    Applicant: IBM

    Inventor： SHAPIRO MICHAEL JAY ,  WASSICK THOMAS ANTHONY ,  INTERRANTE MARIO J ,  LAFONTANT GARY ,  WEBB BUCKNELL C

    IPC: H01L21/283 ,  H01L23/50 ,  H01L21/768

    Abstract: Es wird eine Halbleiterstruktur beschrieben, die eine Vielzahl übereinander gestapelter Halbleiterchips in einer dreidimensionalen Anordnung beinhaltet. Ein erster Halbleiterchip steht in Kontakt mit einem zweiten Halbleiterchip. Der erste Halbleiterchip beinhaltet eine Silicium-Durchkontaktierung (TSV), welche sich durch den ersten Halbleiterchip hindurch erstreckt; eine elektrisch leitende Kontaktfläche an einer Oberfläche des ersten Halbleiterchips, wobei die TSV in Kontakt mit einer ersten Seite der elektrisch leitenden Kontaktfläche endet; eine Passivierungsschicht, welche die elektrisch leitende Kontaktfläche bedeckt, wobei die Passivierungsschicht eine Vielzahl von Öffnungen aufweist; und eine Vielzahl elektrisch leitender Strukturen, welche in der Vielzahl von Öffnungen und in Kontakt mit einer zweiten Seite der elektrisch leitenden Kontaktfläche ausgebildet sind, wobei der Kontakt der Vielzahl elektrisch leitender Strukturen mit der elektrisch leitenden Kontaktfläche in Bezug auf den Kontakt der TSV mit der elektrisch leitenden Kontaktfläche versetzt ist.

    Semiconductor structure to reduce electromigration
    4.
    发明专利
    Semiconductor structure to reduce electromigration 未知

    公开(公告)号：GB2491446B

    公开(公告)日：2013-07-10

    申请号：GB201207700

    申请日：2012-05-02

    Applicant: IBM

    Inventor： SHAPIRO MICHAEL JAY ,  LAFONTANT GARY ,  WASSICK THOMAS ANTHONY ,  WEBB BUCKNELL ,  INTERRANTE MARIO

    IPC: H01L25/065 ,  H01L21/60

    Abstract: A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.

    A contact pad and passivation layer structure offset from a through silicon via to reduce electro-migration.
    5.
    发明专利
    A contact pad and passivation layer structure offset from a through silicon via to reduce electro-migration. 未知

    公开(公告)号：GB2491446A

    公开(公告)日：2012-12-05

    申请号：GB201207700

    申请日：2012-05-02

    Applicant: IBM

    Inventor： SHAPIRO MICHAEL JAY ,  LAFONTANT GARY ,  WASSICK THOMAS ANTHONY ,  WEBB BUCKNELL ,  INTERRANTE MARIO

    IPC: H01L25/065 ,  H01L21/60

    Abstract: The a semiconductor chip 400 includes one or more through silicon vias 410 (TSV) extending through the chip, the via meeting with an electrically conducting pad 416 at the chip surface. A passivation layer 404 covers chip surface and the electrically conducting pad(s) and has a plurality of openings 406 to allow the pad to connect with a electrically conducting structures, such as solder balls 408. The location of the openings is offset with respect to the location 402 of the connection with between the TSV with the electrically conducting pad. The semiconductor chip may have the contacts arranged to allow stacking with a second semiconductor chip in a three dimensional configuration (fig 1). Figures 6 and 7 show how multiple openings reduce current density near the TSV in comparison to a single opening over the TSV, when the openings do not lie over the TSV.

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