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    SOLDER HIERARCHY FOR LEAD FREE SOLDER JOINT
    3.
    发明申请
    SOLDER HIERARCHY FOR LEAD FREE SOLDER JOINT 审中-公开
    用于无铅焊接接头的焊料层级

    公开(公告)号：WO2004026517A3

    公开(公告)日：2004-05-06

    申请号：PCT/US0329092

    申请日：2003-09-12

    Applicant: IBM

    Inventor： INTERRANTE MARIO ,  FARCOOQ MUKTA G ,  SABLINSKI WILLIAM EDWARD

    IPC: B23K1/00 ,  B23K35/14 ,  B23K35/26 ,  B23K101/40 ,  B23K101/42 ,  C22C13/00 ,  H05K3/34 ,  B23K31/02 ,  B23K35/12 ,  B23K35/34

    CPC classification number: B23K1/0016 ,  B23K35/262 ,  B23K2201/36 ,  H01L2224/16225 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613

    Abstract: A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module (20) to a circuit board (120). An off-eutectic solder (60) concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder (60) contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition (60) provides an inter­metallic phase structure in the module side fillet during assembly. The inter­metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns (100) from the board (120) without simultaneous removal from the module (20).

    Abstract translation: 用于电子元件的第二层焊接连接的无铅焊料层次结构，例如将电子模块（20）连接到电路板（120）。 SnCu或SnAg的非共晶焊料（60）浓度用于模块侧连接。 这种非共晶焊料（60）含有足够的金属间化合物以提供模块侧连接，并具有稳健的二级装配和返工工艺。 非共晶组合物（60）在组装期间在模块侧边角中提供金属间相结构。 金属间相结构消除了第二级组装期间的倾斜和塌陷问题，并且通过提供更加粘性的接头允许从板（120）移除柱（100）而无需同时从模块（20）移除而帮助返工。

    SOLDER HIERARCHY FOR LEAD FREE SOLDER JOINT
    5.
    发明专利
    SOLDER HIERARCHY FOR LEAD FREE SOLDER JOINT 未知

    公开(公告)号：AU2003273330A1

    公开(公告)日：2004-04-08

    申请号：AU2003273330

    申请日：2003-09-12

    Applicant: IBM

    Inventor： FARCOOQ MUKTA G ,  SABLINSKI WILLIAM EDWARD ,  INTERRANTE MARIO

    IPC: B23K1/00 ,  B23K35/14 ,  B23K35/26 ,  B23K101/40 ,  B23K101/42 ,  C22C13/00 ,  H05K3/34

    Abstract: A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module to a circuit board. An off-eutectic solder concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition provides an inter-metallic phase structure in the module side fillet during assembly. The inter-metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns from the board without simultaneous removal from the module.

    Solder hierarchy for lead free solder joint
    7.
    发明专利
    Solder hierarchy for lead free solder joint 未知

    公开(公告)号：AU2003273330A8

    公开(公告)日：2004-04-08

    申请号：AU2003273330

    申请日：2003-09-12

    Applicant: IBM

    Inventor： FARCOOQ MUKTA G ,  INTERRANTE MARIO ,  SABLINSKI WILLIAM EDWARD

    IPC: B23K1/00 ,  B23K35/14 ,  B23K35/26 ,  B23K101/40 ,  B23K101/42 ,  C22C13/00 ,  H05K3/34 ,  B23K31/02 ,  B23K35/12 ,  B23K35/34

    Abstract: A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module to a circuit board. An off-eutectic solder concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition provides an inter-metallic phase structure in the module side fillet during assembly. The inter-metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns from the board without simultaneous removal from the module.

    Semiconductor structure to reduce electromigration
    9.
    发明专利
    Semiconductor structure to reduce electromigration 未知

    公开(公告)号：GB2491446B

    公开(公告)日：2013-07-10

    申请号：GB201207700

    申请日：2012-05-02

    Applicant: IBM

    Inventor： SHAPIRO MICHAEL JAY ,  LAFONTANT GARY ,  WASSICK THOMAS ANTHONY ,  WEBB BUCKNELL ,  INTERRANTE MARIO

    IPC: H01L25/065 ,  H01L21/60

    Abstract: A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.

    A contact pad and passivation layer structure offset from a through silicon via to reduce electro-migration.
    10.
    发明专利
    A contact pad and passivation layer structure offset from a through silicon via to reduce electro-migration. 未知

    公开(公告)号：GB2491446A

    公开(公告)日：2012-12-05

    申请号：GB201207700

    申请日：2012-05-02

    Applicant: IBM

    Inventor： SHAPIRO MICHAEL JAY ,  LAFONTANT GARY ,  WASSICK THOMAS ANTHONY ,  WEBB BUCKNELL ,  INTERRANTE MARIO

    IPC: H01L25/065 ,  H01L21/60

    Abstract: The a semiconductor chip 400 includes one or more through silicon vias 410 (TSV) extending through the chip, the via meeting with an electrically conducting pad 416 at the chip surface. A passivation layer 404 covers chip surface and the electrically conducting pad(s) and has a plurality of openings 406 to allow the pad to connect with a electrically conducting structures, such as solder balls 408. The location of the openings is offset with respect to the location 402 of the connection with between the TSV with the electrically conducting pad. The semiconductor chip may have the contacts arranged to allow stacking with a second semiconductor chip in a three dimensional configuration (fig 1). Figures 6 and 7 show how multiple openings reduce current density near the TSV in comparison to a single opening over the TSV, when the openings do not lie over the TSV.

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